finish and test CFA
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.gitignore
vendored
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.gitignore
vendored
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/CFA/sim/**
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!/CFA/sim/demosaic.v
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12
CFA/cfa.v
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CFA/cfa.v
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`timescale 1 ns / 1 ps
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`default_nettype none
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module cfa
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#(
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parameter IM_WIDTH = 1936;
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parameter IM_HEIGHT = 1088;
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)(
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);
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endmodule
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252
CFA/demosaic.v
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CFA/demosaic.v
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module demosaic(clk, reset, in_en, data_in, wr_r, addr_r, wdata_r, rdata_r, wr_g, addr_g, wdata_g, rdata_g, wr_b, addr_b, wdata_b, rdata_b, done);
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input clk;
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input reset;
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input in_en;
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input [7:0] data_in;
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output reg wr_r;
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output reg [13:0] addr_r;
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output reg [7:0] wdata_r;
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input [7:0] rdata_r;
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output reg wr_g;
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output reg [13:0] addr_g;
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output reg [7:0] wdata_g;
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input [7:0] rdata_g;
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output reg wr_b;
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output reg [13:0] addr_b;
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output reg [7:0] wdata_b;
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input [7:0] rdata_b;
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output reg done;
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// Register
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reg [1:0] bilinearCase;
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reg [2:0] state, nextState;
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reg [3:0] counter9;
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reg [6:0] caseCounter, round;
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reg [7:0] data [8:0];
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reg [7:0] red, blue, green;
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reg [14:0] counter, biCounter; // bicounter store the center address
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// State parameter
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localparam READDATA = 0; // Read data, then wirte to wdata
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localparam COLOR = 1; // Choose the case of color
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localparam STORE9 = 2; // Store 9 element to register data
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localparam BILINEAR = 3; // Bilinear Interpolation
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localparam WRITEDATA = 4; // Write data to memory
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localparam FINISH = 5; // Done
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// State control
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always @(posedge clk or posedge reset) begin
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if(reset)
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state <= READDATA;
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else
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state <= nextState;
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end
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//next state logic
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always @(*) begin
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case (state)
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READDATA: nextState = (counter == 15'd16384)? COLOR : READDATA;
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COLOR: nextState = STORE9;
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STORE9: nextState = (counter9 == 4'd9)? BILINEAR : STORE9;
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BILINEAR: nextState = WRITEDATA;
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WRITEDATA: nextState = (biCounter == 15'd16257)? FINISH : COLOR;
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FINISH: nextState = FINISH;
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default: nextState = READDATA;
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endcase
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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done <= 1'd0;
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wr_r <= 1'd0;
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wr_g <= 1'd0;
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wr_b <= 1'd0;
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bilinearCase <= 2'd0;
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counter9 <= 4'd0;
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caseCounter <= 7'd0;
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round <= 7'd0;
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red <= 9'd0;
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blue <= 9'd0;
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green <= 9'd0;
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addr_r <= 14'd0;
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addr_g <= 14'd0;
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addr_b <= 14'd0;
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biCounter <= 15'd129;
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counter <= 15'd0;
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end
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else begin
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case (state)
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READDATA: begin
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if(in_en) begin
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wr_r <= 1'd1;
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wr_g <= 1'd1;
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wr_b <= 1'd1;
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addr_r <= counter;
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addr_g <= counter;
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addr_b <= counter;
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wdata_r <= data_in;
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wdata_g <= data_in;
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wdata_b <= data_in;
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counter <= counter + 1;
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end
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end
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COLOR: begin
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wr_r <= 1'd0;
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wr_g <= 1'd0;
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wr_b <= 1'd0;
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if(!(round & 1)) begin // Even round, 0,2,4,6,8,...
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if(!(caseCounter & 1)) // Even case, 0,2,4,6,8,...
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bilinearCase <= 2'd0;
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else // Odd case, 1,3,5,7,9,...
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bilinearCase <= 2'd1;
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end
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else begin // Odd round, 1,3,5,7,9,...
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if(!(caseCounter & 1)) // Even case, 0,2,4,6,8,...
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bilinearCase <= 2'd2;
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else // Odd case, 1,3,5,7,9,...
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bilinearCase <= 2'd3;
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end
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caseCounter <= caseCounter + 7'd1;
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end
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STORE9: begin
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wr_r <= 1'd0;
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wr_g <= 1'd0;
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wr_b <= 1'd0;
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/*
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* I use R,G,B memory to store pattern data. when in case 0(the middle color is green), I will update the missing blue and red data to memory.
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* In next turn is case 1(the middle color is blue). It will use previous data, but the blue and red data are changed in previous turn. So the
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* previous green data is the origin data.
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*/
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if(counter9 > 4'd0) begin
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case (bilinearCase)
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0: begin
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case (counter9)
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2: data[counter9 - 1] <= rdata_r;
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4: data[counter9 - 1] <= rdata_b;
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default: data[counter9 - 1] <= rdata_g;
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endcase
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end
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1: begin
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case (counter9)
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1,3: data[counter9 - 1] <= rdata_r;
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2,4: data[counter9 - 1] <= rdata_g;
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default: data[counter9 - 1] <= rdata_b;
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endcase
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end
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2: begin
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case (counter9)
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1,3: data[counter9 - 1] <= rdata_b;
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2,4: data[counter9 - 1] <= rdata_g;
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default: data[counter9 - 1] <= rdata_r;
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endcase
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end
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3: begin
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case (counter9)
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2: data[counter9 - 1] <= rdata_b;
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4: data[counter9 - 1] <= rdata_r;
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default: data[counter9 - 1] <= rdata_g;
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endcase
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end
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endcase
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end
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counter9 <= counter9 + 4'd1;
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case (counter9) // For y axis (row)
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0,1,2: begin
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addr_g[13:7] <= biCounter[13:7] - 7'd1;
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addr_r[13:7] <= biCounter[13:7] - 7'd1;
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addr_b[13:7] <= biCounter[13:7] - 7'd1;
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end
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3,4,5: begin
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addr_g[13:7] <= biCounter[13:7];
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addr_r[13:7] <= biCounter[13:7];
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addr_b[13:7] <= biCounter[13:7];
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end
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6,7,8: begin
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addr_g[13:7] <= biCounter[13:7] + 7'd1;
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addr_r[13:7] <= biCounter[13:7] + 7'd1;
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addr_b[13:7] <= biCounter[13:7] + 7'd1;
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end
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endcase
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case (counter9) // For x axis (col)
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0,3,6: begin
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addr_g[6:0] <= biCounter[6:0] - 7'd1;
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addr_r[6:0] <= biCounter[6:0] - 7'd1;
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addr_b[6:0] <= biCounter[6:0] - 7'd1;
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end
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1,4,7: begin
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addr_g[6:0] <= biCounter[6:0];
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addr_r[6:0] <= biCounter[6:0];
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addr_b[6:0] <= biCounter[6:0];
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end
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2,5,8: begin
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addr_g[6:0] <= biCounter[6:0] + 7'd1;
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addr_r[6:0] <= biCounter[6:0] + 7'd1;
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addr_b[6:0] <= biCounter[6:0] + 7'd1;
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end
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endcase
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end
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BILINEAR: begin
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// data case 0 case 1 case 2 case 3
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// 0 1 2 G R G R G R B G B G B G
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// 3 4 5 B G B G B G G R G R G R
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// 6 7 8 G R G R G R B G B G B G
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case (bilinearCase)
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0: begin // Missing B, R on G
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red <= (data[1] + data[7]) / 2;
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blue <= (data[3] + data[5]) / 2;
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green <= data[4];
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end
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1: begin // Missing G, R on B
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green <= (data[1] + data[3] + data[5] + data[7]) / 4;
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red <= (data[0] + data[2] + data[6] + data[8]) / 4;
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blue <= data[4];
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end
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2: begin // Missing G, B on R
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green <= (data[1] + data[3] + data[5] + data[7]) / 4;
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blue <= (data[0] + data[2] + data[6] + data[8]) / 4;
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red <= data[4];
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end
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3: begin // Missing B, R on G
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blue <= (data[1] + data[7]) / 2;
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red <= (data[3] + data[5]) / 2;
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green <= data[4];
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end
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endcase
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end
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WRITEDATA: begin
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wr_r <= 1'd1;
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wr_g <= 1'd1;
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wr_b <= 1'd1;
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addr_r <= biCounter;
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addr_g <= biCounter;
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addr_b <= biCounter;
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wdata_r <= red;
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wdata_g <= green;
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wdata_b <= blue;
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if(caseCounter == 7'd126) begin // Finish one row, then initialize the caseCounter
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caseCounter <= 7'd0;
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round <= round + 7'd1;
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biCounter <= biCounter + 15'd3; // Skip the edge
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end
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else
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biCounter <= biCounter + 15'd1;
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end
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FINISH: begin
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done <= 1'd1;
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end
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endcase
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end
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end
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endmodule
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