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Verilog 60.1%
C++ 25.7%
SystemVerilog 8.8%
Coq 4.8%
CMake 0.4%
Other 0.1%
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SelfConfusion 536bb715b1 finish and test CFA 2024-05-09 22:56:32 +08:00
CFA finish and test CFA 2024-05-09 22:56:32 +08:00
FIFO first commit 2024-05-09 22:36:04 +08:00
sim first commit 2024-05-09 22:36:04 +08:00
.gitignore finish and test CFA 2024-05-09 22:56:32 +08:00
isp.v finish and test CFA 2024-05-09 22:56:32 +08:00