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This repository has been archived on 2026-10-09. You can view files and clone it, but you cannot make any changes to its state, such as pushing and creating new issues, pull requests or comments.
  • Verilog 64.9%
  • C++ 25.7%
  • SystemVerilog 8.8%
  • CMake 0.4%
  • Nix 0.1%
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Repository files (latest commit first)
Filename Latest commit message Latest commit date
2024-11-03 20:38:29 +08:00
rtl fix DPC and reconstruct isp 2024-11-03 20:38:29 +08:00
src fix DPC and reconstruct isp 2024-11-03 20:38:29 +08:00
.envrc switch lsp to clangd and reconstruct project 2024-09-15 22:04:48 +08:00
.gitignore switch lsp to clangd and reconstruct project 2024-09-15 22:04:48 +08:00
.justfile fix DPC and reconstruct isp 2024-11-03 20:38:29 +08:00
.svlint.toml fix DPC and reconstruct isp 2024-11-03 20:38:29 +08:00
.svls.toml fix demosaic not work correctly and polish project manage 2024-10-25 23:12:57 +08:00
CMakeLists.txt fix DPC and reconstruct isp 2024-11-03 20:38:29 +08:00
flake.lock fix demosaic not work correctly and polish project manage 2024-10-25 23:12:57 +08:00
flake.nix add justfile and polish project structure 2024-10-06 20:31:32 +08:00
FPGA.nix fix DPC and reconstruct isp 2024-11-03 20:38:29 +08:00
xmake.lua fix DPC and reconstruct isp 2024-11-03 20:38:29 +08:00