add justfile and polish project structure
This commit is contained in:
parent
c807c24456
commit
f4efa6177e
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@ -0,0 +1,64 @@
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alias c := clean-build
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alias b := build
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alias r := run
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# default target
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default := "Visp_Pipeline"
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# clean all outpu files
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clean-all:
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rm -rf build logs
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# clean build output files
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clean-build:
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rm -rf ./build/*
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# build and run default target
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all: build run
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# clean and build
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rebuild: clean-build build
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# generate build files
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generate:
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cmake . -B ./build/ -G Ninja
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# build default target
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build: generate
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ninja -C ./build/ {{default}} -v
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# build all project
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build-all: generate
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cmake --build ./build/ -v
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# build ISP target
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build-Visp: generate
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cmake --bulid ./build/ -t Visp
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# build ISP Pipeline target
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build-Visp_Pipeline: generate
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cmake --bulid ./build/ -t Visp_Pipeline
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# run default target
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run:
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exec "./build/{{default}}"
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# run ISP
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run-Visp:
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./build/Visp
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# run ISP Pipeline
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run-Visp_Pipeline:
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./build/Visp_Pipeline
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# run default target with tracing wave
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trace:
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exec "./build/{{default}}" +trace
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# run ISP with tracing wave
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trace-Visp:
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./build/Visp +trace
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# run ISP Pipeline with tracing wave
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trace-Visp_Pipeline:
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./build/Visp_Pipeline +trace
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@ -39,19 +39,25 @@ find_package(SystemCLanguage QUIET)
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# file(GLOB_RECURSE IMG_SRC ${PROJECT_SOURCE_DIR}/src/img_process/*.cpp)
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# add_library(img_process STATIC ${IMG_SRC})
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# Set input and output location
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set(INPUT_IMG ${PROJECT_SOURCE_DIR}/src/transform/test.bin)
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set(OUTPUT_DIR ${PROJECT_SOURCE_DIR}/logs/)
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add_compile_definitions(
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INPUT_IMG="${INPUT_IMG}"
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OUTPUT_DIR="${OUTPUT_DIR}"
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)
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# Get RTL source code dir
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SUBDIRLIST(RTL_SUBDIR ${PROJECT_SOURCE_DIR}/rtl)
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# ---------------------- EXE ---------------------------
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# VISP
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# ---------------------- EXE ---------------------------
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add_executable(Visp ${PROJECT_SOURCE_DIR}/src/sc_main.cpp)
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target_compile_definitions(Visp
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PRIVATE INPUT_IMG="${PROJECT_SOURCE_DIR}/src/transform/test.bin"
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PRIVATE OUTPUT_DIR="${PROJECT_SOURCE_DIR}/logs/"
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)
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target_include_directories(Visp PRIVATE ${PROJECT_SOURCE_DIR}/src/img_process)
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# target_link_libraries(Visp PRIVATE img_process)
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# Get RTL source code dir
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SUBDIRLIST(RTL_SUBDIR ${PROJECT_SOURCE_DIR}/rtl)
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# Add the Verilated circuit to the target
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verilate(Visp SYSTEMC COVERAGE TRACE
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INCLUDE_DIRS ${RTL_SUBDIR}
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@ -67,15 +73,13 @@ verilator_link_systemc(Visp)
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# VISP_Pipeline
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# ---------------------- EXE ---------------------------
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add_executable(Visp_Pipeline ${PROJECT_SOURCE_DIR}/src/sc_main_pipeline.cpp)
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target_compile_definitions(Visp_Pipeline
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PRIVATE INPUT_IMG="${PROJECT_SOURCE_DIR}/src/transform/test.bin"
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PRIVATE OUTPUT_DIR="${PROJECT_SOURCE_DIR}/logs/"
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target_include_directories(
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Visp_Pipeline
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PRIVATE ${PROJECT_SOURCE_DIR}/src/img_process
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PRIVATE ${PROJECT_SOURCE_DIR}/src
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)
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target_include_directories(Visp_Pipeline PRIVATE ${PROJECT_SOURCE_DIR}/src/img_process)
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# target_link_libraries(Visp_Pipeline PRIVATE img_process)
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# Get RTL source code dir
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SUBDIRLIST(RTL_SUBDIR ${PROJECT_SOURCE_DIR}/rtl)
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# Add the Verilated circuit to the target
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verilate(Visp_Pipeline SYSTEMC COVERAGE TRACE
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INCLUDE_DIRS ${RTL_SUBDIR}
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@ -85,4 +89,4 @@ verilate(Visp_Pipeline SYSTEMC COVERAGE TRACE
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)
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# SystemC Link
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verilator_link_systemc(Visp_Pipeline)
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verilator_link_systemc(Visp_Pipeline)
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9
FPGA.nix
9
FPGA.nix
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@ -19,6 +19,15 @@
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# Enable languages support
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# languages.cplusplus.enable = true;
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languages.python = {
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enable = true;
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version = "3.11";
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venv.enable = true;
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venv.requirements = ''
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teroshdl
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cocotb
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'';
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};
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# When enter shell, exec ...
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enterShell = ''
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56
flake.lock
56
flake.lock
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@ -191,6 +191,22 @@
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"type": "github"
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}
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},
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"flake-compat_3": {
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"flake": false,
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"locked": {
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"lastModified": 1696426674,
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"narHash": "sha256-kvjfFW7WAETZlt09AgDn1MrtKzP7t90Vf7vypd3OL1U=",
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"owner": "edolstra",
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"repo": "flake-compat",
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"rev": "0f9255e01c2351cc7d116c072cb317785dd33b33",
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"type": "github"
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},
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"original": {
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"owner": "edolstra",
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"repo": "flake-compat",
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"type": "github"
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}
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},
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"flake-parts": {
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"inputs": {
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"nixpkgs-lib": [
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@ -429,6 +445,27 @@
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"type": "github"
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}
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},
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"nixpkgs-python": {
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"inputs": {
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"flake-compat": "flake-compat_3",
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"nixpkgs": [
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"nixpkgs"
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]
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},
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"locked": {
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"lastModified": 1722978926,
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"narHash": "sha256-sqOOEaKJJSUFBzag/cGeeXV491TrrVFY3DFBs1w20V8=",
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"owner": "cachix",
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"repo": "nixpkgs-python",
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"rev": "7c550bca7e6cf95898e32eb2173efe7ebb447460",
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"type": "github"
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},
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"original": {
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"owner": "cachix",
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"repo": "nixpkgs-python",
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"type": "github"
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}
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},
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"nixpkgs-regression": {
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"locked": {
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"lastModified": 1643052045,
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@ -511,14 +548,18 @@
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},
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"nixpkgs_3": {
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"locked": {
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"lastModified": 315532800,
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"narHash": "sha256-DXLcxy2Vmxj0vD/GACAsw/JCeyi3UJlVl/9iU+ZnPnU=",
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"type": "tarball",
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"url": "https://mirrors.ustc.edu.cn/nix-channels/nixpkgs-unstable/nixexprs.tar.xz"
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"lastModified": 1728018373,
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"narHash": "sha256-NOiTvBbRLIOe5F6RbHaAh6++BNjsb149fGZd1T4+KBg=",
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"owner": "NixOS",
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"repo": "nixpkgs",
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"rev": "bc947f541ae55e999ffdb4013441347d83b00feb",
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"type": "github"
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},
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"original": {
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"type": "tarball",
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"url": "https://mirrors.ustc.edu.cn/nix-channels/nixpkgs-unstable/nixexprs.tar.xz"
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"owner": "NixOS",
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"ref": "nixos-unstable",
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"repo": "nixpkgs",
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"type": "github"
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}
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},
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"poetry2nix": {
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@ -614,7 +655,8 @@
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"root": {
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"inputs": {
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"devenv": "devenv",
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"nixpkgs": "nixpkgs_3"
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"nixpkgs": "nixpkgs_3",
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"nixpkgs-python": "nixpkgs-python"
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}
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},
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"systems": {
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@ -1,6 +1,8 @@
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{
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inputs = {
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nixpkgs.url = "https://mirrors.ustc.edu.cn/nix-channels/nixpkgs-unstable/nixexprs.tar.xz";
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nixpkgs.url = "github:NixOS/nixpkgs/nixos-unstable";
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nixpkgs-python.url = "github:cachix/nixpkgs-python";
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nixpkgs-python.inputs.nixpkgs.follows = "nixpkgs";
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devenv.url = "github:cachix/devenv";
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devenv.inputs.nixpkgs.follows = "nixpkgs";
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};
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@ -1,26 +1,26 @@
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`timescale 1ns / 1ps
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module Demosaic_Pipeline #(
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parameter WINDOW_LENGTH = 3,
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parameter reg [15:0] TOTAL_WIDTH = 512+3, // 总图像宽度
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parameter reg [15:0] TOTAL_HEIGHT = 256+3, // 总图像高度
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parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
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parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
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)(
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parameter WINDOW_LENGTH = 3,
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parameter reg [15:0] TOTAL_WIDTH = 512+3, // 总图像宽度
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parameter reg [15:0] TOTAL_HEIGHT = 256+3, // 总图像高度
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parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
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parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
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)(
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input wire clk,
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input wire reset,
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input wire [DATA_WIDTH - 1:0] in_data [WINDOW_LENGTH*WINDOW_LENGTH], // 数据输入线.第一列数据在[0],[1],[2]中
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output reg [DATA_WIDTH - 1:0] out_data [3], // 数据输出线,3、2、1分别表示r、g、b
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input wire in_valid,
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output wire out_valid,
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input wire in_ready,
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output wire out_ready,
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output reg out_hsync, // 行同步,一行第一个像素点输出的同时高电平
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output reg out_fsync // 帧同步,一帧第一个像素点输出的同时高电平
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);
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);
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localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH;
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localparam PIPILINE = 3;
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@ -40,9 +40,12 @@ parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
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reg [1:0] raw_type;
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integer i;
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always @(posedge clk) begin
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if(reset) begin
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for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= 0;
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always @(posedge clk)
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begin
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if(reset)
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begin
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for(i=0;i<DATA_NUM;i=i+1)
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data_cache[i] <= 0;
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pipeline_valid <= 0;
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{red, green, blue} <= 0;
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{out_data[2],out_data[1],out_data[0]} <= 0;
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@ -51,36 +54,45 @@ parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
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pos_y <= ~0;
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temp_pos_x <= 0;
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temp_pos_y <= 0;
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end else if(pipeline_running) begin
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end
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else if(pipeline_running)
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begin
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pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
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if(in_valid) begin
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for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= in_data[i];
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if(in_valid)
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begin
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for(i=0;i<DATA_NUM;i=i+1)
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data_cache[i] <= in_data[i];
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pos_x <= (pos_x >= TOTAL_WIDTH - 1)?(0):(pos_x + 1);
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pos_y <= (pos_x >= TOTAL_WIDTH - 1)?((pos_y >= TOTAL_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
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end
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if(pipeline_valid[0]) begin
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if(pipeline_valid[0])
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begin
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temp_pos_x <= pos_x;
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temp_pos_y <= pos_y;
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case (raw_type)
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0: begin // Missing B, R on G
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0:
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begin // Missing B, R on G
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blue <= (data_cache[1] + data_cache[7]) >> 1;
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red <= (data_cache[3] + data_cache[5]) >> 1;
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green <= data_cache[4];
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end
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1: begin // Missing G, R on B
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1:
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begin // Missing G, R on B
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green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
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red <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
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blue <= data_cache[4];
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end
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2: begin // Missing G, B on R
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2:
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begin // Missing G, B on R
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green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
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blue <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
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red <= data_cache[4];
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end
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3: begin // Missing B, R on G
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3:
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begin // Missing B, R on G
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red <= (data_cache[1] + data_cache[7]) >> 1;
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blue <= (data_cache[3] + data_cache[5]) >> 1;
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green <= data_cache[4];
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@ -88,7 +100,8 @@ parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
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endcase
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end
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if(pipeline_valid[1]) begin
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if(pipeline_valid[1])
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begin
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{out_data[2],out_data[1],out_data[0]} <= {red,blue,green};
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out_hsync <= (temp_pos_x == 0);
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out_fsync <= ((temp_pos_x == 0) && (temp_pos_y == 0));
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@ -98,13 +111,20 @@ parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
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// 0:gr 1:rg 2:bg 3:gb 窗口右移,0<->1 2<->3; 窗口下移,0<->2,1<->3。
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// bg gb gr rg
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always @(*) begin
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if(reset) raw_type = RAW_TYPE;
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else case (RAW_TYPE)
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2'b00: raw_type = {pos_y[0], pos_x[0]};
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2'b01: raw_type = {pos_y[0], ~pos_x[0]};
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2'b10: raw_type = {~pos_y[0], pos_x[0]};
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2'b11: raw_type = {~pos_y[0], ~pos_x[0]};
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always @(*)
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begin
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if(reset)
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raw_type = RAW_TYPE;
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else
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case (RAW_TYPE)
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2'b00:
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raw_type = {pos_y[0], pos_x[0]};
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2'b01:
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raw_type = {pos_y[0], ~pos_x[0]};
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2'b10:
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raw_type = {~pos_y[0], pos_x[0]};
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2'b11:
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raw_type = {~pos_y[0], ~pos_x[0]};
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endcase
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end
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@ -12,7 +12,6 @@
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#include <systemc>
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// Include common routines
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#include <string>
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#include <sys/stat.h> // mkdir
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#include <utility>
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#include <vector>
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@ -22,8 +21,8 @@
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// Include model header, generated from Verilating "isp.v"
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#include "Visp_Pipeline.h"
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// Write Pictures
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#include "bitmap_image.hpp"
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// Include testbench written by systemc
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#include "tb_isp.hpp"
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// Image Parameters
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static const uint16_t IN_WIDTH = 1936;
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|
@ -56,161 +55,6 @@ static const double contrast = 1.2;
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using namespace sc_core;
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using namespace sc_dt;
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SC_MODULE(TB_ISP) {
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sc_in_clk clk;
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sc_in<bool> rst;
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sc_in<bool> in_ready; // next module ready to receive data
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sc_out<bool> out_valid; // next module data valid signal
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sc_out<uint32_t> out_data[3]; // next module receive data
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sc_in<bool> in_valid; // this module receive data valid signal
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sc_out<bool> out_ready; // this module ready to receive data
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sc_in<uint32_t> in_data; // this module receive data
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bool is_done; // when receive all data
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std::vector<uint16_t> image; // the data of image
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std::vector<uint32_t> process_image = std::vector<uint32_t>(
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OUT_SIZE, 0); // after isp process, the data of image
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|
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SC_CTOR(TB_ISP) {
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SC_CTHREAD(sendData, clk.pos()); // when clk posedge, exec sendData
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reset_signal_is(rst, true); // set rst signal
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SC_CTHREAD(readData, clk.pos());
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reset_signal_is(rst, true); // set rst signal
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}
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void sendData(void) {
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// init var
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uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0;
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bool is_finish = false; // when send all data
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// reset
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out_valid = false;
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for (auto &data : out_data)
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data = 0;
|
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|
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while (true) {
|
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if (in_ready && !is_finish) {
|
||||
// valid and send data
|
||||
out_valid = true;
|
||||
out_data[0] = image[(pos_y + 0) * IN_WIDTH + pos_x];
|
||||
out_data[1] = image[(pos_y + 1) * IN_WIDTH + pos_x];
|
||||
out_data[2] = image[(pos_y + 2) * IN_WIDTH + pos_x];
|
||||
|
||||
// print data
|
||||
std::printf("x=%4d, y=%4d, data=0x%04x\t", pos_x, pos_y,
|
||||
image[(pos_y + 0) * IN_WIDTH + pos_x]);
|
||||
std::printf("x=%4d, y=%4d, data=0x%04x\t", pos_x, pos_y,
|
||||
image[(pos_y + 1) * IN_WIDTH + pos_x]);
|
||||
std::printf("x=%4d, y=%4d, data=0x%04x\n", pos_x, pos_y,
|
||||
image[(pos_y + 2) * IN_WIDTH + pos_x]);
|
||||
pos_x++;
|
||||
|
||||
// calculate position and recognize when to finish
|
||||
if (pos_x >= IN_WIDTH) {
|
||||
pos_x = 0;
|
||||
pos_y++;
|
||||
}
|
||||
if (pos_y >= IN_HEIGHT - 1) {
|
||||
pos_y = 0;
|
||||
cnt_flame++;
|
||||
}
|
||||
if (cnt_flame >= FLAMES) {
|
||||
is_finish = true;
|
||||
}
|
||||
} else {
|
||||
out_valid = false;
|
||||
}
|
||||
|
||||
// wait for next clk
|
||||
wait();
|
||||
}
|
||||
}
|
||||
|
||||
void readData(void) {
|
||||
// init local var
|
||||
uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0;
|
||||
uint32_t last_data = 0, cnt = 0;
|
||||
bool is_finish = false;
|
||||
// reset
|
||||
out_ready = false;
|
||||
is_done = false;
|
||||
|
||||
while (true) {
|
||||
if (!is_finish) {
|
||||
out_ready = true;
|
||||
|
||||
// when data valid, write it down
|
||||
if (in_valid) {
|
||||
process_image[pos_y * OUT_WIDTH + pos_x] = in_data;
|
||||
|
||||
// calculate position
|
||||
pos_x++;
|
||||
|
||||
if (pos_x >= OUT_WIDTH) {
|
||||
pos_x = 0;
|
||||
pos_y++;
|
||||
}
|
||||
if (pos_y >= OUT_HEIGHT) {
|
||||
pos_y = 0;
|
||||
saveData(
|
||||
("output_img_" + std::to_string(cnt_flame) + ".bmp").c_str());
|
||||
cnt_flame++;
|
||||
}
|
||||
if (cnt_flame >= FLAMES) {
|
||||
is_finish = true;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
out_ready = false;
|
||||
}
|
||||
|
||||
// when no data send, give finish signal
|
||||
if (is_finish && (last_data == in_data)) {
|
||||
cnt++;
|
||||
if (cnt >= 100000L) { // when receive many times the same data
|
||||
is_done = true;
|
||||
std::printf("Finish Reading data; pos_x = %d, pos_y = %d\n", pos_x,
|
||||
pos_y);
|
||||
}
|
||||
} else {
|
||||
cnt = 0;
|
||||
}
|
||||
last_data = in_data;
|
||||
|
||||
// wait for next clk
|
||||
wait();
|
||||
}
|
||||
}
|
||||
|
||||
bool saveData(const char *name) {
|
||||
bool ret = true;
|
||||
|
||||
// Check Image Size
|
||||
if (process_image.size() > OUT_SIZE) {
|
||||
std::cout << "Process Image Over Size!!!\n"
|
||||
<< "Image Size:" << process_image.size() << "\n";
|
||||
return false;
|
||||
}
|
||||
|
||||
// Write BMP image
|
||||
bitmap_image bmp(OUT_WIDTH, OUT_HEIGHT);
|
||||
if (!bmp) {
|
||||
std::cout << "Output Image Open Failed!!!\n";
|
||||
return false;
|
||||
}
|
||||
for (int y = 0; y < OUT_HEIGHT; y++)
|
||||
for (int x = 0; x < OUT_WIDTH; x++)
|
||||
bmp.set_pixel(x, y,
|
||||
(process_image[y * OUT_WIDTH + x] & 0x00ff0000) >> 16,
|
||||
(process_image[y * OUT_WIDTH + x] & 0x0000ff00) >> 8,
|
||||
(process_image[y * OUT_WIDTH + x] & 0x000000ff) >> 0);
|
||||
bmp.save_image(std::string(OUTPUT_DIR) + name);
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
|
||||
int sc_main(int argc, char *argv[]) {
|
||||
std::printf("Enter into sc_main\n");
|
||||
|
||||
|
@ -314,7 +158,7 @@ int sc_main(int argc, char *argv[]) {
|
|||
isp.gain_blue(gain_blue);
|
||||
|
||||
// Construct testbench module
|
||||
TB_ISP tb_isp("tb_isp");
|
||||
TB_ISP tb_isp("tb_isp", IN_WIDTH, IN_HEIGHT, OUT_WIDTH, OUT_HEIGHT, FLAMES, OUTPUT_DIR);
|
||||
tb_isp.image = std::move(in_image);
|
||||
tb_isp.clk(clk);
|
||||
tb_isp.rst(rst);
|
||||
|
|
|
@ -0,0 +1,180 @@
|
|||
#ifndef __TB_ISP_H__
|
||||
#define __TB_ISP_H__
|
||||
|
||||
#include <cstdint>
|
||||
#include <systemc>
|
||||
|
||||
// Write Pictures
|
||||
#include "bitmap_image.hpp"
|
||||
|
||||
SC_MODULE(TB_ISP) {
|
||||
sc_core::sc_in_clk clk;
|
||||
sc_core::sc_in<bool> rst;
|
||||
|
||||
sc_core::sc_in<bool> in_ready; // next module ready to receive data
|
||||
sc_core::sc_out<bool> out_valid; // next module data valid signal
|
||||
sc_core::sc_out<uint32_t> out_data[3]; // next module receive data
|
||||
|
||||
sc_core::sc_in<bool> in_valid; // this module receive data valid signal
|
||||
sc_core::sc_out<bool> out_ready; // this module ready to receive data
|
||||
sc_core::sc_in<uint32_t> in_data; // this module receive data
|
||||
|
||||
const uint16_t IN_WIDTH;
|
||||
const uint16_t IN_HEIGHT;
|
||||
const uint32_t IN_SIZE;
|
||||
const uint16_t OUT_WIDTH;
|
||||
const uint16_t OUT_HEIGHT;
|
||||
const uint32_t OUT_SIZE;
|
||||
const uint32_t FLAMES;
|
||||
const std::string OUT_DIR;
|
||||
|
||||
bool is_done; // when receive all data
|
||||
std::vector<uint16_t> image; // the data of image
|
||||
std::vector<uint32_t> process_image; // after isp process, the data of image
|
||||
|
||||
SC_CTOR(TB_ISP, const uint16_t in_width, const uint16_t in_height,
|
||||
const uint16_t out_width, const uint16_t out_height,
|
||||
const uint32_t cnt_flame, const std::string& out_dir)
|
||||
: IN_WIDTH(in_width), IN_HEIGHT(in_height), IN_SIZE(in_width * in_height),
|
||||
OUT_WIDTH(out_width), OUT_HEIGHT(out_height),
|
||||
OUT_SIZE(out_width * out_height), FLAMES(cnt_flame),
|
||||
OUT_DIR(out_dir),
|
||||
process_image(std::vector<uint32_t>(out_width * out_height, 0)) {
|
||||
SC_CTHREAD(sendData, clk.pos()); // when clk posedge, exec sendData
|
||||
reset_signal_is(rst, true); // set rst signal
|
||||
|
||||
SC_CTHREAD(readData, clk.pos());
|
||||
reset_signal_is(rst, true); // set rst signal
|
||||
}
|
||||
|
||||
void sendData(void) {
|
||||
// init var
|
||||
uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0;
|
||||
bool is_finish = false; // when send all data
|
||||
// reset
|
||||
out_valid = false;
|
||||
for (auto &data : out_data)
|
||||
data = 0;
|
||||
|
||||
while (true) {
|
||||
if (in_ready && !is_finish) {
|
||||
// valid and send data
|
||||
out_valid = true;
|
||||
out_data[0] = image[(pos_y + 0) * IN_WIDTH + pos_x];
|
||||
out_data[1] = image[(pos_y + 1) * IN_WIDTH + pos_x];
|
||||
out_data[2] = image[(pos_y + 2) * IN_WIDTH + pos_x];
|
||||
|
||||
// print data
|
||||
std::printf("x=%4d, y=%4d, data=0x%04x\t", pos_x, pos_y,
|
||||
image[(pos_y + 0) * IN_WIDTH + pos_x]);
|
||||
std::printf("x=%4d, y=%4d, data=0x%04x\t", pos_x, pos_y,
|
||||
image[(pos_y + 1) * IN_WIDTH + pos_x]);
|
||||
std::printf("x=%4d, y=%4d, data=0x%04x\n", pos_x, pos_y,
|
||||
image[(pos_y + 2) * IN_WIDTH + pos_x]);
|
||||
pos_x++;
|
||||
|
||||
// calculate position and recognize when to finish
|
||||
if (pos_x >= IN_WIDTH) {
|
||||
pos_x = 0;
|
||||
pos_y++;
|
||||
}
|
||||
if (pos_y >= IN_HEIGHT - 1) {
|
||||
pos_y = 0;
|
||||
cnt_flame++;
|
||||
}
|
||||
if (cnt_flame >= FLAMES) {
|
||||
is_finish = true;
|
||||
}
|
||||
} else {
|
||||
out_valid = false;
|
||||
}
|
||||
|
||||
// wait for next clk
|
||||
wait();
|
||||
}
|
||||
}
|
||||
|
||||
void readData(void) {
|
||||
// init local var
|
||||
uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0;
|
||||
uint32_t last_data = 0, cnt = 0;
|
||||
bool is_finish = false;
|
||||
// reset
|
||||
out_ready = false;
|
||||
is_done = false;
|
||||
|
||||
while (true) {
|
||||
if (!is_finish) {
|
||||
out_ready = true;
|
||||
|
||||
// when data valid, write it down
|
||||
if (in_valid) {
|
||||
process_image[pos_y * OUT_WIDTH + pos_x] = in_data;
|
||||
|
||||
// calculate position
|
||||
pos_x++;
|
||||
|
||||
if (pos_x >= OUT_WIDTH) {
|
||||
pos_x = 0;
|
||||
pos_y++;
|
||||
}
|
||||
if (pos_y >= OUT_HEIGHT) {
|
||||
pos_y = 0;
|
||||
saveData(
|
||||
("output_img_" + std::to_string(cnt_flame) + ".bmp").c_str());
|
||||
cnt_flame++;
|
||||
}
|
||||
if (cnt_flame >= FLAMES) {
|
||||
is_finish = true;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
out_ready = false;
|
||||
}
|
||||
|
||||
// when no data send, give finish signal
|
||||
if (is_finish && (last_data == in_data)) {
|
||||
cnt++;
|
||||
if (cnt >= 100000L) { // when receive many times the same data
|
||||
is_done = true;
|
||||
std::printf("Finish Reading data; pos_x = %d, pos_y = %d\n", pos_x,
|
||||
pos_y);
|
||||
}
|
||||
} else {
|
||||
cnt = 0;
|
||||
}
|
||||
last_data = in_data;
|
||||
|
||||
// wait for next clk
|
||||
wait();
|
||||
}
|
||||
}
|
||||
|
||||
bool saveData(const char *name) {
|
||||
bool ret = true;
|
||||
|
||||
// Check Image Size
|
||||
if (process_image.size() > OUT_SIZE) {
|
||||
std::cout << "Process Image Over Size!!!\n"
|
||||
<< "Image Size:" << process_image.size() << "\n";
|
||||
return false;
|
||||
}
|
||||
|
||||
// Write BMP image
|
||||
bitmap_image bmp(OUT_WIDTH, OUT_HEIGHT);
|
||||
if (!bmp) {
|
||||
std::cout << "Output Image Open Failed!!!\n";
|
||||
return false;
|
||||
}
|
||||
for (int y = 0; y < OUT_HEIGHT; y++)
|
||||
for (int x = 0; x < OUT_WIDTH; x++)
|
||||
bmp.set_pixel(x, y,
|
||||
(process_image[y * OUT_WIDTH + x] & 0x00ff0000) >> 16,
|
||||
(process_image[y * OUT_WIDTH + x] & 0x0000ff00) >> 8,
|
||||
(process_image[y * OUT_WIDTH + x] & 0x000000ff) >> 0);
|
||||
bmp.save_image(std::string(OUT_DIR) + name);
|
||||
return ret;
|
||||
}
|
||||
};
|
||||
|
||||
#endif
|
Loading…
Reference in New Issue