SikongJueluo
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ISP
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50 Commits 1 Branch 0 Tags 11 MiB
Verilog 60.1%
C++ 25.7%
SystemVerilog 8.8%
Coq 4.8%
CMake 0.4%
Other 0.1%
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SikongJueluo f4efa6177e
add justfile and polish project structure 		2024-10-06 20:31:32 +08:00
rtl add justfile and polish project structure 2024-10-06 20:31:32 +08:00
src add justfile and polish project structure 2024-10-06 20:31:32 +08:00
.envrc switch lsp to clangd and reconstruct project 2024-09-15 22:04:48 +08:00
.gitignore switch lsp to clangd and reconstruct project 2024-09-15 22:04:48 +08:00
.justfile add justfile and polish project structure 2024-10-06 20:31:32 +08:00
CMakeLists.txt add justfile and polish project structure 2024-10-06 20:31:32 +08:00
FPGA.nix add justfile and polish project structure 2024-10-06 20:31:32 +08:00
flake.lock add justfile and polish project structure 2024-10-06 20:31:32 +08:00
flake.nix add justfile and polish project structure 2024-10-06 20:31:32 +08:00
xmake.lua isp pipeline pass sim 2024-10-03 17:06:40 +08:00