first commit
This commit is contained in:
SelfConfusion
commit
25032efc34
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@ -0,0 +1,12 @@
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`timescale 1 ns / 1 ps
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`default_nettype none
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module cfa
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#(
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parameter IM_WIDTH = 1936;
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parameter IM_HEIGHT = 1088;
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)(
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);
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endmodule
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async_fifo.v
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fifomem.v
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fifomem_dp.v
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hdl.list
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rptr_empty.v
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sync_ptr.v
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sync_r2w.v
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sync_w2r.v
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wptr_full.v
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// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module async_fifo
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#(
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parameter DSIZE = 8,
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parameter ASIZE = 4,
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parameter FALLTHROUGH = "TRUE" // First word fall-through without latency
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)(
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input wire wclk,
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input wire wrst_n,
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input wire winc,
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input wire [DSIZE-1:0] wdata,
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output wire wfull,
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output wire awfull,
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input wire rclk,
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input wire rrst_n,
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input wire rinc,
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output wire [DSIZE-1:0] rdata,
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output wire rempty,
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output wire arempty
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);
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wire [ASIZE-1:0] waddr, raddr;
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wire [ASIZE :0] wptr, rptr, wq2_rptr, rq2_wptr;
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// The module synchronizing the read point
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// from read to write domain
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sync_r2w
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#(ASIZE)
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sync_r2w (
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.wq2_rptr (wq2_rptr),
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.rptr (rptr),
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.wclk (wclk),
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.wrst_n (wrst_n)
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);
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// The module synchronizing the write point
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// from write to read domain
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sync_w2r
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#(ASIZE)
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sync_w2r (
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.rq2_wptr (rq2_wptr),
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.wptr (wptr),
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.rclk (rclk),
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.rrst_n (rrst_n)
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);
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// The module handling the write requests
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wptr_full
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#(ASIZE)
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wptr_full (
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.awfull (awfull),
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.wfull (wfull),
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.waddr (waddr),
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.wptr (wptr),
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.wq2_rptr (wq2_rptr),
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.winc (winc),
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.wclk (wclk),
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.wrst_n (wrst_n)
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);
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// The DC-RAM
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fifomem
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#(DSIZE, ASIZE, FALLTHROUGH)
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fifomem (
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.rclken (rinc),
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.rclk (rclk),
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.rdata (rdata),
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.wdata (wdata),
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.waddr (waddr),
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.raddr (raddr),
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.wclken (winc),
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.wfull (wfull),
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.wclk (wclk)
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);
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// The module handling read requests
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rptr_empty
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#(ASIZE)
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rptr_empty (
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.arempty (arempty),
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.rempty (rempty),
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.raddr (raddr),
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.rptr (rptr),
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.rq2_wptr (rq2_wptr),
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.rinc (rinc),
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.rclk (rclk),
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.rrst_n (rrst_n)
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);
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endmodule
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`resetall
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// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module fifomem
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#(
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parameter DATASIZE = 8, // Memory data word width
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parameter ADDRSIZE = 4, // Number of mem address bits
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parameter FALLTHROUGH = "TRUE" // First word fall-through
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) (
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input wire wclk,
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input wire wclken,
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input wire [ADDRSIZE-1:0] waddr,
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input wire [DATASIZE-1:0] wdata,
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input wire wfull,
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input wire rclk,
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input wire rclken,
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input wire [ADDRSIZE-1:0] raddr,
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output wire [DATASIZE-1:0] rdata
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);
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localparam DEPTH = 1<<ADDRSIZE;
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reg [DATASIZE-1:0] mem [0:DEPTH-1];
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reg [DATASIZE-1:0] rdata_r;
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always @(posedge wclk) begin
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if (wclken && !wfull)
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mem[waddr] <= wdata;
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end
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generate
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if (FALLTHROUGH == "TRUE")
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begin : fallthrough
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assign rdata = mem[raddr];
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end
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else
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begin : registered_read
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always @(posedge rclk) begin
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if (rclken)
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rdata_r <= mem[raddr];
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end
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assign rdata = rdata_r;
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end
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endgenerate
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endmodule
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`resetall
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//-----------------------------------------------------------------------------
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// Copyright 2017 Damien Pretet ThotIP
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// Copyright 2018 Julius Baxter
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//-----------------------------------------------------------------------------
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`timescale 1 ns / 1 ps
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`default_nettype none
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module fifomem_dp
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#(
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parameter DATASIZE = 8, // Memory data word width
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parameter ADDRSIZE = 4, // Number of mem address bits
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parameter FALLTHROUGH = "TRUE" // First word fall-through
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) (
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input wire a_clk,
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input wire [DATASIZE-1:0] a_wdata,
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output wire [DATASIZE-1:0] a_rdata,
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input wire [ADDRSIZE-1:0] a_addr,
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input wire a_rinc,
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input wire a_winc,
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input wire b_clk,
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input wire [DATASIZE-1:0] b_wdata,
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output wire [DATASIZE-1:0] b_rdata,
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input wire [ADDRSIZE-1:0] b_addr,
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input wire b_rinc,
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input wire b_winc
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);
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reg [DATASIZE-1:0] a_rdata_r;
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reg [DATASIZE-1:0] b_rdata_r;
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generate
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localparam DEPTH = 1<<ADDRSIZE;
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reg [DATASIZE-1:0] mem [0:DEPTH-1];
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if (FALLTHROUGH == "TRUE") begin : fallthrough
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always @(posedge a_clk)
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if (a_winc)
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mem[a_addr] <= a_wdata;
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assign a_rdata = mem[a_addr];
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always @(posedge b_clk)
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if (b_winc)
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mem[b_addr] <= b_wdata;
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assign b_rdata = mem[b_addr];
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end else begin : registered
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wire a_en = a_rinc | a_winc;
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always @(posedge a_clk)
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if (a_en) begin
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if (a_winc)
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mem[a_addr] <= a_wdata;
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a_rdata_r <= mem[a_addr];
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end
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assign a_rdata = a_rdata_r;
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wire b_en = b_rinc | b_winc;
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always @(posedge b_clk)
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if (b_en) begin
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if (b_winc)
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mem[b_addr] <= b_wdata;
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b_rdata_r <= mem[b_addr];
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end
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assign b_rdata = b_rdata_r;
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end // block: registered
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endgenerate
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endmodule
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`resetall
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// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module rptr_empty
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#(
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parameter ADDRSIZE = 4
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)(
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input wire rclk,
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input wire rrst_n,
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input wire rinc,
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input wire [ADDRSIZE :0] rq2_wptr,
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output reg rempty,
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output reg arempty,
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output wire [ADDRSIZE-1:0] raddr,
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output reg [ADDRSIZE :0] rptr
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);
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reg [ADDRSIZE:0] rbin;
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wire [ADDRSIZE:0] rgraynext, rbinnext, rgraynextm1;
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wire arempty_val, rempty_val;
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//-------------------
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// GRAYSTYLE2 pointer
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//-------------------
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always @(posedge rclk or negedge rrst_n) begin
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if (!rrst_n)
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{rbin, rptr} <= 0;
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else
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{rbin, rptr} <= {rbinnext, rgraynext};
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end
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// Memory read-address pointer (okay to use binary to address memory)
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assign raddr = rbin[ADDRSIZE-1:0];
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assign rbinnext = rbin + (rinc & ~rempty);
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assign rgraynext = (rbinnext >> 1) ^ rbinnext;
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assign rgraynextm1 = ((rbinnext + 1'b1) >> 1) ^ (rbinnext + 1'b1);
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//---------------------------------------------------------------
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// FIFO empty when the next rptr == synchronized wptr or on reset
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//---------------------------------------------------------------
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assign rempty_val = (rgraynext == rq2_wptr);
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assign arempty_val = (rgraynextm1 == rq2_wptr);
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always @ (posedge rclk or negedge rrst_n) begin
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if (!rrst_n) begin
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arempty <= 1'b0;
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rempty <= 1'b1;
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end
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else begin
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arempty <= arempty_val;
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rempty <= rempty_val;
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end
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end
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endmodule
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`resetall
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@ -0,0 +1,30 @@
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// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module sync_ptr
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#(
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parameter ASIZE = 4
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)(
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input wire dest_clk,
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input wire dest_rst_n,
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input wire [ASIZE:0] src_ptr,
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output reg [ASIZE:0] dest_ptr
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);
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reg [ASIZE:0] ptr_x;
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always @(posedge dest_clk or negedge dest_rst_n) begin
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if (!dest_rst_n)
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{dest_ptr,ptr_x} <= 0;
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else
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{dest_ptr,ptr_x} <= {ptr_x,src_ptr};
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end
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endmodule
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`resetall
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@ -0,0 +1,31 @@
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// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module sync_r2w
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#(
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parameter ASIZE = 4
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)(
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input wire wclk,
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input wire wrst_n,
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input wire [ASIZE:0] rptr,
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output reg [ASIZE:0] wq2_rptr
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);
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reg [ASIZE:0] wq1_rptr;
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always @(posedge wclk or negedge wrst_n) begin
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if (!wrst_n)
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{wq2_rptr,wq1_rptr} <= 0;
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else
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{wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
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end
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endmodule
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`resetall
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@ -0,0 +1,31 @@
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// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module sync_w2r
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#(
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parameter ASIZE = 4
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)(
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input wire rclk,
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input wire rrst_n,
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output reg [ASIZE:0] rq2_wptr,
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input wire [ASIZE:0] wptr
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);
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reg [ASIZE:0] rq1_wptr;
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always @(posedge rclk or negedge rrst_n) begin
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if (!rrst_n)
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{rq2_wptr,rq1_wptr} <= 0;
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else
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{rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
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end
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endmodule
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`resetall
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|
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@ -0,0 +1,65 @@
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// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module wptr_full
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#(
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parameter ADDRSIZE = 4
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)(
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input wire wclk,
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input wire wrst_n,
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input wire winc,
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input wire [ADDRSIZE :0] wq2_rptr,
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output reg wfull,
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output reg awfull,
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output wire [ADDRSIZE-1:0] waddr,
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output reg [ADDRSIZE :0] wptr
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);
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reg [ADDRSIZE:0] wbin;
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wire [ADDRSIZE:0] wgraynext, wbinnext, wgraynextp1;
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wire awfull_val, wfull_val;
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// GRAYSTYLE2 pointer
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always @(posedge wclk or negedge wrst_n) begin
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if (!wrst_n)
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{wbin, wptr} <= 0;
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else
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{wbin, wptr} <= {wbinnext, wgraynext};
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end
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// Memory write-address pointer (okay to use binary to address memory)
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assign waddr = wbin[ADDRSIZE-1:0];
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assign wbinnext = wbin + (winc & ~wfull);
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assign wgraynext = (wbinnext >> 1) ^ wbinnext;
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assign wgraynextp1 = ((wbinnext + 1'b1) >> 1) ^ (wbinnext + 1'b1);
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//------------------------------------------------------------------
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// Simplified version of the three necessary full-tests:
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// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
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// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
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// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
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//------------------------------------------------------------------
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assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
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assign awfull_val = (wgraynextp1 == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
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always @(posedge wclk or negedge wrst_n) begin
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|
||||
if (!wrst_n) begin
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awfull <= 1'b0;
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wfull <= 1'b0;
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end else begin
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awfull <= awfull_val;
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wfull <= wfull_val;
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end
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end
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|
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endmodule
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`resetall
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|
|
@ -0,0 +1,33 @@
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|||
`include "isp.v"
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`default_nettype none
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||||
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||||
module tb_isp;
|
||||
reg clk;
|
||||
reg rst_n;
|
||||
|
||||
isp
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||||
(
|
||||
.rst_n (rst_n),
|
||||
.clk (clk),
|
||||
);
|
||||
|
||||
localparam CLK_PERIOD = 10;
|
||||
always #(CLK_PERIOD/2) clk=~clk;
|
||||
|
||||
// initial begin
|
||||
// $dumpfile("tb_isp.vcd");
|
||||
// $dumpvars(0, tb_isp);
|
||||
// end
|
||||
|
||||
initial begin
|
||||
#1 rst_n<=1'bx;clk<=1'bx;
|
||||
#(CLK_PERIOD*3) rst_n<=1;
|
||||
#(CLK_PERIOD*3) rst_n<=0;clk<=0;
|
||||
|
||||
|
||||
|
||||
$finish(2);
|
||||
end
|
||||
|
||||
endmodule
|
||||
`default_nettype wire
|
||||
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