commit 25032efc3409b56540739e2095bcb7c1042a5298
Author: SelfConfusion <1822250894@qq.com>
Date:   Thu May 9 22:36:04 2024 +0800

    first commit

diff --git a/CFA/cfa.v b/CFA/cfa.v
new file mode 100644
index 0000000..d6b1502
--- /dev/null
+++ b/CFA/cfa.v
@@ -0,0 +1,12 @@
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module cfa
+#(
+    parameter IM_WIDTH = 1936;
+    parameter IM_HEIGHT = 1088;
+)(
+    
+);
+    
+endmodule
\ No newline at end of file
diff --git a/FIFO/async_fifo.list b/FIFO/async_fifo.list
new file mode 100644
index 0000000..7167c4f
--- /dev/null
+++ b/FIFO/async_fifo.list
@@ -0,0 +1,9 @@
+async_fifo.v
+fifomem.v
+fifomem_dp.v
+hdl.list
+rptr_empty.v
+sync_ptr.v
+sync_r2w.v
+sync_w2r.v
+wptr_full.v
diff --git a/FIFO/async_fifo.v b/FIFO/async_fifo.v
new file mode 100644
index 0000000..77661e3
--- /dev/null
+++ b/FIFO/async_fifo.v
@@ -0,0 +1,98 @@
+// distributed under the mit license
+// https://opensource.org/licenses/mit-license.php
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module async_fifo
+
+    #(
+        parameter DSIZE = 8,
+        parameter ASIZE = 4,
+        parameter FALLTHROUGH = "TRUE" // First word fall-through without latency
+    )(
+        input  wire             wclk,
+        input  wire             wrst_n,
+        input  wire             winc,
+        input  wire [DSIZE-1:0] wdata,
+        output wire             wfull,
+        output wire             awfull,
+        input  wire             rclk,
+        input  wire             rrst_n,
+        input  wire             rinc,
+        output wire [DSIZE-1:0] rdata,
+        output wire             rempty,
+        output wire             arempty
+    );
+
+    wire [ASIZE-1:0] waddr, raddr;
+    wire [ASIZE  :0] wptr, rptr, wq2_rptr, rq2_wptr;
+
+    // The module synchronizing the read point
+    // from read to write domain
+    sync_r2w
+    #(ASIZE)
+    sync_r2w (
+    .wq2_rptr (wq2_rptr),
+    .rptr     (rptr),
+    .wclk     (wclk),
+    .wrst_n   (wrst_n)
+    );
+
+    // The module synchronizing the write point
+    // from write to read domain
+    sync_w2r
+    #(ASIZE)
+    sync_w2r (
+    .rq2_wptr (rq2_wptr),
+    .wptr     (wptr),
+    .rclk     (rclk),
+    .rrst_n   (rrst_n)
+    );
+
+    // The module handling the write requests
+    wptr_full
+    #(ASIZE)
+    wptr_full (
+    .awfull   (awfull),
+    .wfull    (wfull),
+    .waddr    (waddr),
+    .wptr     (wptr),
+    .wq2_rptr (wq2_rptr),
+    .winc     (winc),
+    .wclk     (wclk),
+    .wrst_n   (wrst_n)
+    );
+
+    // The DC-RAM
+    fifomem
+    #(DSIZE, ASIZE, FALLTHROUGH)
+    fifomem (
+    .rclken (rinc),
+    .rclk   (rclk),
+    .rdata  (rdata),
+    .wdata  (wdata),
+    .waddr  (waddr),
+    .raddr  (raddr),
+    .wclken (winc),
+    .wfull  (wfull),
+    .wclk   (wclk)
+    );
+
+    // The module handling read requests
+    rptr_empty
+    #(ASIZE)
+    rptr_empty (
+    .arempty  (arempty),
+    .rempty   (rempty),
+    .raddr    (raddr),
+    .rptr     (rptr),
+    .rq2_wptr (rq2_wptr),
+    .rinc     (rinc),
+    .rclk     (rclk),
+    .rrst_n   (rrst_n)
+    );
+
+endmodule
+
+`resetall
diff --git a/FIFO/fifomem.v b/FIFO/fifomem.v
new file mode 100644
index 0000000..e69d9d1
--- /dev/null
+++ b/FIFO/fifomem.v
@@ -0,0 +1,52 @@
+// distributed under the mit license
+// https://opensource.org/licenses/mit-license.php
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module fifomem
+
+    #(
+        parameter  DATASIZE = 8,    // Memory data word width
+        parameter  ADDRSIZE = 4,    // Number of mem address bits
+        parameter  FALLTHROUGH = "TRUE" // First word fall-through
+    ) (
+        input  wire                wclk,
+        input  wire                wclken,
+        input  wire [ADDRSIZE-1:0] waddr,
+        input  wire [DATASIZE-1:0] wdata,
+        input  wire                wfull,
+        input  wire                rclk,
+        input  wire                rclken,
+        input  wire [ADDRSIZE-1:0] raddr,
+        output wire [DATASIZE-1:0] rdata
+    );
+
+    localparam DEPTH = 1<<ADDRSIZE;
+
+    reg [DATASIZE-1:0] mem [0:DEPTH-1];
+    reg [DATASIZE-1:0] rdata_r;
+
+    always @(posedge wclk) begin
+        if (wclken && !wfull)
+            mem[waddr] <= wdata;
+    end
+
+    generate
+        if (FALLTHROUGH == "TRUE")
+        begin : fallthrough
+            assign rdata = mem[raddr];
+        end
+        else
+        begin : registered_read
+            always @(posedge rclk) begin
+                if (rclken)
+                    rdata_r <= mem[raddr];
+            end
+            assign rdata = rdata_r;
+        end
+    endgenerate
+
+endmodule
+
+`resetall
diff --git a/FIFO/fifomem_dp.v b/FIFO/fifomem_dp.v
new file mode 100644
index 0000000..7e2bc36
--- /dev/null
+++ b/FIFO/fifomem_dp.v
@@ -0,0 +1,95 @@
+//-----------------------------------------------------------------------------
+// Copyright 2017 Damien Pretet ThotIP
+// Copyright 2018 Julius Baxter
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//-----------------------------------------------------------------------------
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module fifomem_dp
+
+    #(
+        parameter  DATASIZE     = 8,      // Memory data word width
+        parameter  ADDRSIZE     = 4,      // Number of mem address bits
+        parameter  FALLTHROUGH  = "TRUE"  // First word fall-through
+    ) (
+        input  wire                a_clk,
+        input  wire [DATASIZE-1:0] a_wdata,
+        output wire [DATASIZE-1:0] a_rdata,
+        input  wire [ADDRSIZE-1:0] a_addr,
+        input  wire                a_rinc,
+        input  wire                a_winc,
+
+        input  wire                b_clk,
+        input  wire [DATASIZE-1:0] b_wdata,
+        output wire [DATASIZE-1:0] b_rdata,
+        input  wire [ADDRSIZE-1:0] b_addr,
+        input  wire                b_rinc,
+        input  wire                b_winc
+    );
+
+    reg [DATASIZE-1:0] a_rdata_r;
+    reg [DATASIZE-1:0] b_rdata_r;
+
+    generate
+
+        localparam DEPTH = 1<<ADDRSIZE;
+        reg [DATASIZE-1:0] mem [0:DEPTH-1];
+
+        if (FALLTHROUGH == "TRUE") begin : fallthrough
+
+            always @(posedge a_clk)
+                if (a_winc)
+                    mem[a_addr] <= a_wdata;
+
+            assign a_rdata  = mem[a_addr];
+
+            always @(posedge b_clk)
+                if (b_winc)
+                    mem[b_addr] <= b_wdata;
+
+            assign b_rdata = mem[b_addr];
+
+        end else begin : registered
+
+            wire a_en = a_rinc | a_winc;
+
+            always @(posedge a_clk)
+                if (a_en) begin
+                    if (a_winc)
+                        mem[a_addr] <= a_wdata;
+                    a_rdata_r <= mem[a_addr];
+                end
+
+            assign a_rdata = a_rdata_r;
+
+            wire b_en = b_rinc | b_winc;
+
+            always @(posedge b_clk)
+                if (b_en) begin
+                    if (b_winc)
+                        mem[b_addr] <= b_wdata;
+                    b_rdata_r <= mem[b_addr];
+                end
+
+            assign b_rdata = b_rdata_r;
+
+        end // block: registered
+    endgenerate
+
+
+endmodule
+
+`resetall
diff --git a/FIFO/rptr_empty.v b/FIFO/rptr_empty.v
new file mode 100644
index 0000000..17269c5
--- /dev/null
+++ b/FIFO/rptr_empty.v
@@ -0,0 +1,65 @@
+// distributed under the mit license
+// https://opensource.org/licenses/mit-license.php
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module rptr_empty
+
+    #(
+    parameter ADDRSIZE = 4
+    )(
+    input  wire                rclk,
+    input  wire                rrst_n,
+    input  wire                rinc,
+    input  wire [ADDRSIZE  :0] rq2_wptr,
+    output reg                 rempty,
+    output reg                 arempty,
+    output wire [ADDRSIZE-1:0] raddr,
+    output reg  [ADDRSIZE  :0] rptr
+    );
+
+    reg  [ADDRSIZE:0] rbin;
+    wire [ADDRSIZE:0] rgraynext, rbinnext, rgraynextm1;
+    wire              arempty_val, rempty_val;
+
+    //-------------------
+    // GRAYSTYLE2 pointer
+    //-------------------
+    always @(posedge rclk or negedge rrst_n) begin
+
+        if (!rrst_n)
+            {rbin, rptr} <= 0;
+        else
+            {rbin, rptr} <= {rbinnext, rgraynext};
+
+    end
+
+    // Memory read-address pointer (okay to use binary to address memory)
+    assign raddr     = rbin[ADDRSIZE-1:0];
+    assign rbinnext  = rbin + (rinc & ~rempty);
+    assign rgraynext = (rbinnext >> 1) ^ rbinnext;
+    assign rgraynextm1 = ((rbinnext + 1'b1) >> 1) ^ (rbinnext + 1'b1);
+
+    //---------------------------------------------------------------
+    // FIFO empty when the next rptr == synchronized wptr or on reset
+    //---------------------------------------------------------------
+    assign rempty_val = (rgraynext == rq2_wptr);
+    assign arempty_val = (rgraynextm1 == rq2_wptr);
+
+    always @ (posedge rclk or negedge rrst_n) begin
+
+        if (!rrst_n) begin
+            arempty <= 1'b0;
+            rempty <= 1'b1;
+        end
+        else begin
+            arempty <= arempty_val;
+            rempty <= rempty_val;
+        end
+
+    end
+
+endmodule
+
+`resetall
diff --git a/FIFO/sync_ptr.v b/FIFO/sync_ptr.v
new file mode 100644
index 0000000..416bbb8
--- /dev/null
+++ b/FIFO/sync_ptr.v
@@ -0,0 +1,30 @@
+// distributed under the mit license
+// https://opensource.org/licenses/mit-license.php
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module sync_ptr
+
+    #(
+    parameter ASIZE = 4
+    )(
+    input  wire              dest_clk,
+    input  wire              dest_rst_n,
+    input  wire [ASIZE:0] src_ptr,
+    output reg  [ASIZE:0] dest_ptr
+    );
+
+    reg [ASIZE:0] ptr_x;
+
+    always @(posedge dest_clk or negedge dest_rst_n) begin
+
+        if (!dest_rst_n)
+            {dest_ptr,ptr_x} <= 0;
+        else
+            {dest_ptr,ptr_x} <= {ptr_x,src_ptr};
+    end
+
+endmodule
+
+`resetall
diff --git a/FIFO/sync_r2w.v b/FIFO/sync_r2w.v
new file mode 100644
index 0000000..05d65fe
--- /dev/null
+++ b/FIFO/sync_r2w.v
@@ -0,0 +1,31 @@
+// distributed under the mit license
+// https://opensource.org/licenses/mit-license.php
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module sync_r2w
+
+    #(
+    parameter ASIZE = 4
+    )(
+    input  wire              wclk,
+    input  wire              wrst_n,
+    input  wire [ASIZE:0] rptr,
+    output reg  [ASIZE:0] wq2_rptr
+    );
+
+    reg [ASIZE:0] wq1_rptr;
+
+    always @(posedge wclk or negedge wrst_n) begin
+
+        if (!wrst_n)
+            {wq2_rptr,wq1_rptr} <= 0;
+        else
+            {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
+
+    end
+
+endmodule
+
+`resetall
diff --git a/FIFO/sync_w2r.v b/FIFO/sync_w2r.v
new file mode 100644
index 0000000..396250b
--- /dev/null
+++ b/FIFO/sync_w2r.v
@@ -0,0 +1,31 @@
+// distributed under the mit license
+// https://opensource.org/licenses/mit-license.php
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module sync_w2r
+
+    #(
+    parameter ASIZE = 4
+    )(
+    input  wire              rclk,
+    input  wire              rrst_n,
+    output reg  [ASIZE:0] rq2_wptr,
+    input  wire [ASIZE:0] wptr
+    );
+
+    reg [ASIZE:0] rq1_wptr;
+
+    always @(posedge rclk or negedge rrst_n) begin
+
+        if (!rrst_n)
+            {rq2_wptr,rq1_wptr} <= 0;
+        else
+            {rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};
+
+    end
+
+endmodule
+
+`resetall
diff --git a/FIFO/wptr_full.v b/FIFO/wptr_full.v
new file mode 100644
index 0000000..3c8258c
--- /dev/null
+++ b/FIFO/wptr_full.v
@@ -0,0 +1,65 @@
+// distributed under the mit license
+// https://opensource.org/licenses/mit-license.php
+
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+module wptr_full
+
+	#(
+		parameter ADDRSIZE = 4
+	)(
+		input  wire                wclk,
+		input  wire                wrst_n,
+		input  wire                winc,
+		input  wire [ADDRSIZE  :0] wq2_rptr,
+		output reg                 wfull,
+		output reg                 awfull,
+		output wire [ADDRSIZE-1:0] waddr,
+		output reg  [ADDRSIZE  :0] wptr
+	);
+
+    reg  [ADDRSIZE:0] wbin;
+    wire [ADDRSIZE:0] wgraynext, wbinnext, wgraynextp1;
+    wire              awfull_val, wfull_val;
+
+	// GRAYSTYLE2 pointer
+	always @(posedge wclk or negedge wrst_n) begin
+
+		if (!wrst_n)
+			{wbin, wptr} <= 0;
+		else
+			{wbin, wptr} <= {wbinnext, wgraynext};
+
+	end
+
+    // Memory write-address pointer (okay to use binary to address memory)
+    assign waddr = wbin[ADDRSIZE-1:0];
+    assign wbinnext  = wbin + (winc & ~wfull);
+    assign wgraynext = (wbinnext >> 1) ^ wbinnext;
+    assign wgraynextp1 = ((wbinnext + 1'b1) >> 1) ^ (wbinnext + 1'b1);
+
+    //------------------------------------------------------------------
+    // Simplified version of the three necessary full-tests:
+    // assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
+    //                   (wgnext[ADDRSIZE-1]  !=wq2_rptr[ADDRSIZE-1]) &&
+    // (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
+    //------------------------------------------------------------------
+
+     assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
+     assign awfull_val = (wgraynextp1 == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
+
+     always @(posedge wclk or negedge wrst_n) begin
+
+        if (!wrst_n) begin
+            awfull <= 1'b0;
+            wfull  <= 1'b0;
+        end else begin
+            awfull <= awfull_val;
+            wfull  <= wfull_val;
+        end
+    end
+
+endmodule
+
+`resetall
diff --git a/isp.v b/isp.v
new file mode 100644
index 0000000..e69de29
diff --git a/sim/tb_isp.v b/sim/tb_isp.v
new file mode 100644
index 0000000..c20cf52
--- /dev/null
+++ b/sim/tb_isp.v
@@ -0,0 +1,33 @@
+`include "isp.v"
+`default_nettype none
+
+module tb_isp;
+reg clk;
+reg rst_n;
+
+ isp
+(
+    .rst_n (rst_n),
+    .clk (clk),
+);
+
+localparam CLK_PERIOD = 10;
+always #(CLK_PERIOD/2) clk=~clk;
+
+// initial begin
+//     $dumpfile("tb_isp.vcd");
+//     $dumpvars(0, tb_isp);
+// end
+
+initial begin
+    #1 rst_n<=1'bx;clk<=1'bx;
+    #(CLK_PERIOD*3) rst_n<=1;
+    #(CLK_PERIOD*3) rst_n<=0;clk<=0;
+
+
+
+    $finish(2);
+end
+
+endmodule
+`default_nettype wire
\ No newline at end of file