SikongJueluo
/
ISP
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix DPC and reconstruct isp

This commit is contained in:
SikongJueluo 2024-11-03 20:38:29 +08:00
parent a8fa609228
commit 42f6cdbbda
No known key found for this signature in database
41 changed files with 25742 additions and 693 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
.justfile
View File

@ -67,3 +67,7 @@ trace-Visp:
# run ISP Pipeline with tracing wave # run ISP Pipeline with tracing wave
trace-Visp_Pipeline: trace-Visp_Pipeline:
./build/Visp_Pipeline +trace ./build/Visp_Pipeline +trace
test module: generate
ninja -C ./build/ {{module}}
exec "./build/{{module}}" +trace

13
.svlint.toml
View File

@ -3,7 +3,7 @@ textrules.style_textwidth = true
textrules.style_semicolon = true textrules.style_semicolon = true
option.indent = 2 option.indent = 2
syntaxrules.tab_character = true syntaxrules.tab_character = true
syntaxrules.style_indent = true syntaxrules.style_indent = false
syntaxrules.multiline_if_begin = true syntaxrules.multiline_if_begin = true
syntaxrules.multiline_for_begin = true syntaxrules.multiline_for_begin = true
syntaxrules.style_trailingwhitespace = true syntaxrules.style_trailingwhitespace = true
@ -26,7 +26,7 @@ syntaxrules.eventlist_or = true
syntaxrules.blocking_assignment_in_always_ff = true syntaxrules.blocking_assignment_in_always_ff = true
syntaxrules.blocking_assignment_in_always_latch = true syntaxrules.blocking_assignment_in_always_latch = true
syntaxrules.non_blocking_assignment_in_always_comb = true syntaxrules.non_blocking_assignment_in_always_comb = true
syntaxrules.case_default = true syntaxruleg.case_default = true
syntaxrules.enum_with_type = true syntaxrules.enum_with_type = true
syntaxrules.function_with_automatic = true syntaxrules.function_with_automatic = true
syntaxrules.keyword_forbidden_priority = true syntaxrules.keyword_forbidden_priority = true
@ -80,18 +80,17 @@ syntaxrules.re_forbidden_task = false
syntaxrules.lowercamelcase_package = true syntaxrules.lowercamelcase_package = true
syntaxrules.uppercamelcase_module = true syntaxrules.uppercamelcase_module = true
option.prefix_interface = "ifc_" option.prefix_interface = "ifc_"
syntaxrules.prefix_interface = true syntaxrules.prefix_interface = false
option.prefix_instance = "u_" option.prefix_instance = "u_"
syntaxrules.prefix_instance = true syntaxrules.prefix_instance = true
option.prefix_label = "l_" option.prefix_label = ".*"
syntaxrules.generate_case_with_label = true syntaxrules.generate_case_with_label = true
syntaxrules.generate_for_with_label = true syntaxrules.generate_for_with_label = true
syntaxrules.generate_if_with_label = true
option.prefix_inout = "b_" option.prefix_inout = "b_"
syntaxrules.prefix_inout = true syntaxrules.prefix_inout = true
option.prefix_input = "in_" option.prefix_input = "i_"
syntaxrules.prefix_input = true syntaxrules.prefix_input = true
option.prefix_output = "out_" option.prefix_output = "o_"
syntaxrules.prefix_output = true syntaxrules.prefix_output = true
option.re_required_port_interface = "^[a-z]+[a-zA-Z0-9_]*$" option.re_required_port_interface = "^[a-z]+[a-zA-Z0-9_]*$"
syntaxrules.re_required_port_interface = true syntaxrules.re_required_port_interface = true

44
CMakeLists.txt
View File

@ -6,7 +6,7 @@ project(ISP CXX)
# Add Macro to get all subdir # Add Macro to get all subdir
MACRO(SUBDIRLIST result curdir) MACRO(SUBDIRLIST result curdir)
FILE(GLOB children RELATIVE ${curdir} ${curdir}/*) FILE(GLOB children RELATIVE ${curdir} ${curdir}/*)
SET(dirlist "") SET(dirlist ${curdir})
FOREACH(child ${children}) FOREACH(child ${children})
IF(IS_DIRECTORY ${curdir}/${child}) IF(IS_DIRECTORY ${curdir}/${child})
LIST(APPEND dirlist ${curdir}/${child}) LIST(APPEND dirlist ${curdir}/${child})
@ -41,6 +41,11 @@ if(NOT TARGET spdlog)
find_package(spdlog REQUIRED) find_package(spdlog REQUIRED)
endif() endif()
# Find zlib
if(NOT TARGET ZLIB)
find_package(ZLIB REQUIRED)
endif()
# Create software image process library # Create software image process library
# file(GLOB_RECURSE IMG_SRC ${PROJECT_SOURCE_DIR}/src/img_process/*.cpp) # file(GLOB_RECURSE IMG_SRC ${PROJECT_SOURCE_DIR}/src/img_process/*.cpp)
# add_library(img_process STATIC ${IMG_SRC}) # add_library(img_process STATIC ${IMG_SRC})
@ -58,19 +63,21 @@ add_compile_definitions(
# Get RTL source code dir # Get RTL source code dir
SUBDIRLIST(RTL_SUBDIR ${PROJECT_SOURCE_DIR}/rtl) SUBDIRLIST(RTL_SUBDIR ${PROJECT_SOURCE_DIR}/rtl)
set(VERILATOR_ARGS +librescan +libext+.v+.sv+.vh+.svh -y . -x-assign fast --timing -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-BLKANDNBLK -Wno-SELRANGE)
# ---------------------- EXE --------------------------- # ---------------------- EXE ---------------------------
# Visp # Visp
# ---------------------- EXE --------------------------- # ---------------------- EXE ---------------------------
add_executable(Visp ${PROJECT_SOURCE_DIR}/src/sc_main.cpp) add_executable(Visp ${PROJECT_SOURCE_DIR}/src/sc_main.cpp)
target_include_directories(Visp PRIVATE ${PROJECT_SOURCE_DIR}/src/img_process) target_include_directories(Visp PRIVATE ${PROJECT_SOURCE_DIR}/src/img_process)
target_link_libraries(Visp PRIVATE spdlog::spdlog $<$<BOOL:${MINGW}>:ws2_32>) target_link_libraries(Visp PRIVATE spdlog::spdlog $<$<BOOL:${MINGW}>:ws2_32> PRIVATE ZLIB::ZLIB)
# target_link_libraries(Visp PRIVATE img_process) # target_link_libraries(Visp PRIVATE img_process)
# Add the Verilated circuit to the target # Add the Verilated circuit to the target
verilate(Visp SYSTEMC COVERAGE TRACE verilate(Visp SYSTEMC COVERAGE TRACE
INCLUDE_DIRS ${RTL_SUBDIR} INCLUDE_DIRS ${RTL_SUBDIR}
VERILATOR_ARGS +librescan +libext+.v+.sv+.vh+.svh -y . -x-assign fast VERILATOR_ARGS ${VERILATOR_ARGS}
SOURCES ${PROJECT_SOURCE_DIR}/rtl/isp.sv SOURCES ${PROJECT_SOURCE_DIR}/rtl/isp.sv
TOP_MODULE isp TOP_MODULE isp
) )
@ -86,17 +93,40 @@ target_include_directories(
Visp_Pipeline Visp_Pipeline
PRIVATE ${PROJECT_SOURCE_DIR}/src/img_process PRIVATE ${PROJECT_SOURCE_DIR}/src/img_process
PRIVATE ${PROJECT_SOURCE_DIR}/src PRIVATE ${PROJECT_SOURCE_DIR}/src
PRIVATE ${ZLIB_INCLUDE_DIR}
) )
target_link_libraries(Visp_Pipeline PRIVATE spdlog::spdlog $<$<BOOL:${MINGW}>:ws2_32>) target_link_libraries(Visp_Pipeline PRIVATE ZLIB::ZLIB PRIVATE spdlog::spdlog $<$<BOOL:${MINGW}>:ws2_32>)
# target_link_libraries(Visp_Pipeline PRIVATE img_process) # target_link_libraries(Visp_Pipeline PRIVATE img_process)
# Add the Verilated circuit to the target # Add the Verilated circuit to the target
verilate(Visp_Pipeline SYSTEMC COVERAGE TRACE verilate(Visp_Pipeline SYSTEMC COVERAGE TRACE_FST TRACE_THREADS 4 THREADS 12
INCLUDE_DIRS ${RTL_SUBDIR} INCLUDE_DIRS ${RTL_SUBDIR}
VERILATOR_ARGS +librescan +libext+.v+.sv+.vh+.svh -y . -x-assign fast -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC VERILATOR_ARGS ${VERILATOR_ARGS}
SOURCES ${PROJECT_SOURCE_DIR}/rtl/isp_Pipeline.sv SOURCES ${PROJECT_SOURCE_DIR}/rtl/isp_Pipeline.sv ${PROJECT_SOURCE_DIR}/rtl/SimLib/prim_sim.v
TOP_MODULE isp_Pipeline TOP_MODULE isp_Pipeline
) )
# SystemC Link # SystemC Link
verilator_link_systemc(Visp_Pipeline) verilator_link_systemc(Visp_Pipeline)
# ---------------------- EXE ---------------------------
# VWindows
# ---------------------- EXE ---------------------------
add_executable(VWindows ${PROJECT_SOURCE_DIR}/src/modules_tb/windows_tb.cpp)
target_include_directories(
VWindows
PRIVATE ${ZLIB_INCLUDE_DIR}
)
target_link_libraries(VWindows PRIVATE ZLIB::ZLIB PRIVATE spdlog::spdlog $<$<BOOL:${MINGW}>:ws2_32>)
# target_link_libraries(VWindows PRIVATE img_process)
# Add the Verilated circuit to the target
verilate(VWindows SYSTEMC COVERAGE TRACE_FST TRACE_THREADS 4 THREADS 12
INCLUDE_DIRS ${RTL_SUBDIR}
VERILATOR_ARGS ${VERILATOR_ARGS}
SOURCES ${PROJECT_SOURCE_DIR}/rtl/BayerProcess/Windows_tb.sv ${PROJECT_SOURCE_DIR}/rtl/SimLib/prim_sim.v
TOP_MODULE Windows_tb
)
# SystemC Link
verilator_link_systemc(VWindows)

3
FPGA.nix
View File

@ -4,8 +4,10 @@
# FPGA # FPGA
verilator verilator
systemc systemc
verilog
verible verible
svls svls
zlib
# C/C++ # C/C++
xmake xmake
@ -37,6 +39,7 @@
export SYSTEMC_INCLUDE="${pkgs.systemc}/include" export SYSTEMC_INCLUDE="${pkgs.systemc}/include"
export SYSTEMC_LIBDIR="${pkgs.systemc}/lib" export SYSTEMC_LIBDIR="${pkgs.systemc}/lib"
export VERILATOR_INCLUDE="${pkgs.verilator}/share/verilator/include" export VERILATOR_INCLUDE="${pkgs.verilator}/share/verilator/include"
alias gtkwave="GDK_BACKEND=x11 gtkwave"
echo echo
verilator --version verilator --version
echo echo

239
rtl/BayerProcess/DPC.sv
View File

@ -1,17 +1,17 @@
`timescale 1ns / 1ps
module DPC #( module DPC #(
parameter reg [15:0] TOTAL_WIDTH = 512 + 3, // 总图像宽度
parameter reg [15:0] TOTAL_HEIGHT = 256 + 3, // 总图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值 parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽 parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
parameter reg signed [15:0] THRESHOLD = 30, // 阈值
parameter reg [ 4:0] MODULE_ENABLE = 0, // 是否启用该模块，DEBUG用 parameter reg [ 4:0] MODULE_ENABLE = 0, // 是否启用该模块，DEBUG用
parameter reg [ 4:0] LABLE_ENABLE = 1 // 是否启动坏点标注，DEBUG用 parameter reg [ 4:0] LABLE_ENABLE= 1 // 0:不启用标注, 1:启用标注, 2:启用方向标注
)( )(
input wire clk, input wire clk,
input wire reset, input wire reset,
input wire [DATA_WIDTH - 1:0] in_data [5*5], input wire [DATA_WIDTH - 1:0] in_data [5*5],
input wire [7:0] in_user,
output reg [DATA_WIDTH - 1:0] out_data, output reg [DATA_WIDTH - 1:0] out_data,
output wire [7:0] out_user,
input wire in_valid, input wire in_valid,
output wire out_valid, output wire out_valid,
@ -22,9 +22,10 @@ module DPC #(
localparam WINDOW_LENGTH = 5; localparam WINDOW_LENGTH = 5;
localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH; localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH;
localparam EXPAND_BITS = 5; localparam EXPAND_BITS = 1;
localparam PIPILINE = 9; localparam PIPILINE = 9;
reg [7:0] pipeline_user[PIPILINE];
reg [PIPILINE-1:0] pipeline_valid; reg [PIPILINE-1:0] pipeline_valid;
wire pipeline_running; wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1]; assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
@ -33,40 +34,38 @@ module DPC #(
assign out_ready = pipeline_running; assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高 //out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = pipeline_valid[PIPILINE-1]; assign out_valid = pipeline_valid[PIPILINE-1];
assign out_user = pipeline_user[PIPILINE-1];
reg [DATA_WIDTH-1:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn reg signed [DATA_WIDTH-1+EXPAND_BITS:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [DATA_WIDTH-1:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn reg signed [DATA_WIDTH-1+EXPAND_BITS:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [DATA_WIDTH-1:0] channel_cache[9]; // 缓存颜色通道数据，channel_cache[4]就是中心像素点 reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache[9]; // 缓存颜色通道数据，channel_cache[4]就是中心像素点
reg [DATA_WIDTH-1:0] reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache0,channel_cache1,channel_cache2,channel_cache3,channel_cache4; // 缓存中心像素点的颜色数据
channel_cache0, reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache[3], grad_v_cache[3], grad_i_cache[3], grad_t_cache[3];
channel_cache1, reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache0[3], grad_v_cache0[3], grad_i_cache0[3], grad_t_cache0[3];
channel_cache2, reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache1[3], grad_v_cache1[3], grad_i_cache1[3], grad_t_cache1[3];
channel_cache3, reg signed [DATA_WIDTH-1+EXPAND_BITS+2:0] grad_cache_excute[4];
channel_cache4; // 缓存中心像素点的颜色数据 reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_cache_center[4];
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache_correct[4], channel_cache_correct1[4], channel_cache_correct2[4];
grad_h_cache[3], grad_v_cache[3], grad_45_cache[3], grad_135_cache[3]; reg signed [DATA_WIDTH-1+EXPAND_BITS+EXPAND_BITS:0] channel_cache_correct0[4];
reg [DATA_WIDTH-1+EXPAND_BITS:0] reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_median_cache[4];
grad_h_cache0[3], grad_v_cache0[3], grad_45_cache0[3], grad_135_cache0[3]; reg [1:0] flag_which_dict, dic2;
reg [DATA_WIDTH-1+EXPAND_BITS:0]
grad_h_cache1[3], grad_v_cache1[3], grad_45_cache1[3], grad_135_cache1[3];
reg [DATA_WIDTH-1+EXPAND_BITS:0]
grad_h_cache2[3], grad_v_cache2[3], grad_45_cache2[3], grad_135_cache2[3];
reg [DATA_WIDTH-1+EXPAND_BITS:0] grad_median_cache[4];
reg [1:0] flag_which_dict;
reg [DATA_WIDTH-1:0]
channel_cache_correct[4],
channel_cache_correct0[4],
channel_cache_correct1[4],
channel_cache_correct2[4];
reg [DATA_WIDTH-1:0] channel_cache_correct_final; reg [DATA_WIDTH-1:0] channel_cache_correct_final;
reg flag_if_need_corection; reg flag_if_need_corection;
reg [15:0] pos_x; reg pos_x, pos_y;
reg pos_y_bit;
reg [1:0] raw_type; reg [1:0] raw_type;
/*
-------h
|\ i
| \/
| /\
|/ \
v t
*/
integer i; integer i;
always @(posedge clk) begin always @(posedge clk) begin
if(reset) begin if(reset) begin
for(i=0;i<PIPILINE;i=i+1) pipeline_user[i] <= 0;
for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= 0; for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= 0;
for(i=0;i<DATA_NUM;i=i+1) data_cache0[i] <= 0; for(i=0;i<DATA_NUM;i=i+1) data_cache0[i] <= 0;
for(i=0;i<9;i=i+1) channel_cache[i] <= 0; for(i=0;i<9;i=i+1) channel_cache[i] <= 0;
@ -76,52 +75,47 @@ module DPC #(
channel_cache3 <= 0; channel_cache3 <= 0;
channel_cache4 <= 0; channel_cache4 <= 0;
channel_cache_correct_final <= 0; channel_cache_correct_final <= 0;
for (i = 0; i < 3; i = i + 1) grad_h_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_h_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_h_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_h_cache1[i] <= 0; for(i=0;i<3;i=i+1);
for (i = 0; i < 3; i = i + 1) grad_h_cache1[i] <= 0; for(i=0;i<3;i=i+1) grad_v_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_v_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_v_cache1[i] <= 0; for(i=0;i<3;i=i+1);
for (i = 0; i < 3; i = i + 1) grad_h_cache2[i] <= 0; for(i=0;i<3;i=i+1) grad_i_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_i_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_i_cache1[i] <= 0; for(i=0;i<3;i=i+1);
for (i = 0; i < 3; i = i + 1) grad_v_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_t_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_t_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_t_cache1[i] <= 0; for(i=0;i<3;i=i+1);
for (i = 0; i < 3; i = i + 1) grad_v_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_v_cache2[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_45_cache[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_45_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_45_cache2[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_135_cache[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_135_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_135_cache2[i] <= 0;
for(i=0;i<3;i=i+1) grad_median_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_median_cache[i] <= 0;
for(i=0;i<4;i=i+1) grad_cache_excute[i] <= 0;
for(i=0;i<4;i=i+1) grad_cache_center[i] <= 0;
flag_which_dict <= 0; flag_which_dict <= 0;
flag_if_need_corection <= 0; flag_if_need_corection <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct[i] <= 0; for(i=0;i<4;i=i+1) channel_cache_correct[i] <= 0; for(i=0;i<4;i=i+1) channel_cache_correct1[i] <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct1[i] <= 0; for(i=0;i<4;i=i+1) channel_cache_correct0[i] <= 0;for(i=0;i<4;i=i+1) channel_cache_correct2[i] <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct0[i] <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct2[i] <= 0;
pipeline_valid <= 0; pipeline_valid <= 0;
out_data <= 0; out_data <= 0;
pos_x <= ~0; pos_x <= 0;
pos_y_bit <= ~0; pos_y <= 0;
raw_type <= RAW_TYPE; raw_type <= RAW_TYPE;
end else if(pipeline_running) begin end else if(pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid}; pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if(in_valid) begin if(in_valid) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= in_data[i]; for(i=0;i<DATA_NUM;i=i+1) data_cache0[i] <= {{(EXPAND_BITS){1'b0}},in_data[i]};
pos_x <= (pos_x >= TOTAL_WIDTH - 1) ? (0) : (pos_x + 1); pipeline_user[0] <= in_user;
pos_y_bit <= (pos_x >= TOTAL_WIDTH - 1) ? (~pos_y_bit) : (pos_y_bit); pos_x <= (in_user[0])?(0):(~pos_x);
pos_y <= (in_user[0])?((in_user[1])?(0):(~pos_y)):(pos_y);
end end
if(pipeline_valid[0]) begin if(pipeline_valid[0]) begin
for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= data_cache0[i]; for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= data_cache0[i];
pipeline_user[1] <= pipeline_user[0];
case (RAW_TYPE) case (RAW_TYPE)
2'b00: raw_type <= {pos_y_bit, pos_x[0]}; 2'b00: raw_type <= { pos_y, pos_x};
2'b01: raw_type <= {pos_y_bit, ~pos_x[0]}; 2'b01: raw_type <= { pos_y, ~pos_x};
2'b10: raw_type <= {~pos_y_bit, pos_x[0]}; 2'b10: raw_type <= {~pos_y, pos_x};
2'b11: raw_type <= {~pos_y_bit, ~pos_x[0]}; 2'b11: raw_type <= {~pos_y, ~pos_x};
endcase endcase
end end
if(pipeline_valid[1]) begin if(pipeline_valid[1]) begin
pipeline_user[2] <= pipeline_user[1];
case (raw_type) case (raw_type)
1,2: begin 1,2: begin
channel_cache[0] <= data_cache[00]; channel_cache[0] <= data_cache[00];
@ -149,20 +143,21 @@ module DPC #(
end end
if(pipeline_valid[2]) begin //计算梯度，同时开始校正后数据的部分计算 if(pipeline_valid[2]) begin //计算梯度，同时开始校正后数据的部分计算
pipeline_user[3] <= pipeline_user[2];
channel_cache0 <= channel_cache[4]; channel_cache0 <= channel_cache[4];
grad_h_cache[0] <= channel_cache[0] + channel_cache[2] - 2 * channel_cache[1]; grad_h_cache[0] <= channel_cache[0]/2 + channel_cache[2]/2 - channel_cache[1];
grad_h_cache[1] <= channel_cache[3] + channel_cache[5] - 2 * channel_cache[4]; grad_h_cache[1] <= channel_cache[3]/2 + channel_cache[5]/2 - channel_cache[4];
grad_h_cache[2] <= channel_cache[6] + channel_cache[8] - 2 * channel_cache[7]; grad_h_cache[2] <= channel_cache[6]/2 + channel_cache[8]/2 - channel_cache[7];
grad_v_cache[0] <= channel_cache[0] + channel_cache[6] - 2 * channel_cache[3]; grad_v_cache[0] <= channel_cache[0]/2 + channel_cache[6]/2 - channel_cache[3];
grad_v_cache[1] <= channel_cache[1] + channel_cache[7] - 2 * channel_cache[4]; grad_v_cache[1] <= channel_cache[1]/2 + channel_cache[7]/2 - channel_cache[4];
grad_v_cache[2] <= channel_cache[2] + channel_cache[8] - 2 * channel_cache[5]; grad_v_cache[2] <= channel_cache[2]/2 + channel_cache[8]/2 - channel_cache[5];
grad_45_cache[0] <= 2 * (channel_cache[1] - channel_cache[3]); grad_i_cache[0] <= channel_cache[1]/2 - channel_cache[3]/2;
grad_45_cache[1] <= channel_cache[6] + channel_cache[2] - 2 * channel_cache[4]; grad_i_cache[1] <= channel_cache[6]/2 + channel_cache[2]/2 - channel_cache[4];
grad_45_cache[2] <= 2 * (channel_cache[7] - channel_cache[5]); grad_i_cache[2] <= channel_cache[5]/2 - channel_cache[7]/2;
grad_135_cache[0] <= 2 * (channel_cache[1] - channel_cache[5]); grad_t_cache[0] <= channel_cache[1]/2 - channel_cache[5]/2;
grad_135_cache[1] <= channel_cache[0] + channel_cache[8] - 2 * channel_cache[4]; grad_t_cache[1] <= channel_cache[0]/2 + channel_cache[8]/2 - channel_cache[4];
grad_135_cache[2] <= 2 * (channel_cache[3] - channel_cache[7]); grad_t_cache[2] <= channel_cache[3]/2 - channel_cache[7]/2;
channel_cache_correct[0] <= channel_cache[3]/2 + channel_cache[5]/2; channel_cache_correct[0] <= channel_cache[3]/2 + channel_cache[5]/2;
channel_cache_correct[1] <= channel_cache[1]/2 + channel_cache[7]/2; channel_cache_correct[1] <= channel_cache[1]/2 + channel_cache[7]/2;
@ -170,91 +165,100 @@ module DPC #(
channel_cache_correct[3] <= channel_cache[0]/2 + channel_cache[8]/2; channel_cache_correct[3] <= channel_cache[0]/2 + channel_cache[8]/2;
end end
if(pipeline_valid[3]) begin //计算绝对值，同时完成校正后数据的计算,注意grad_h_cache等是singed，可能为负数 if(pipeline_valid[3]) begin //计算绝对值，同时完成校正后数据的计算
pipeline_user[4] <= pipeline_user[3];
channel_cache1 <= channel_cache0; channel_cache1 <= channel_cache0;
grad_h_cache0 [0] <= grad_h_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [0] + 1) : (grad_h_cache [0]); for(i=0;i<3;i=i+1) grad_h_cache0[i] <= (grad_h_cache[i] < 0) ? (-grad_h_cache[i]) : (grad_h_cache[i]);
grad_h_cache0 [1] <= grad_h_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [1] + 1) : (grad_h_cache [1]); for(i=0;i<3;i=i+1) grad_v_cache0[i] <= (grad_v_cache[i] < 0) ? (-grad_v_cache[i]) : (grad_v_cache[i]);
grad_h_cache0 [2] <= grad_h_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [2] + 1) : (grad_h_cache [2]); for(i=0;i<3;i=i+1) grad_i_cache0[i] <= (grad_i_cache[i] < 0) ? (-grad_i_cache[i]) : (grad_i_cache[i]);
grad_v_cache0 [0] <= grad_v_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [0] + 1) : (grad_v_cache [0]); for(i=0;i<3;i=i+1) grad_t_cache0[i] <= (grad_t_cache[i] < 0) ? (-grad_t_cache[i]) : (grad_t_cache[i]);
grad_v_cache0 [1] <= grad_v_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [1] + 1) : (grad_v_cache [1]); channel_cache_correct0[0] <= channel_cache_correct[0] - grad_h_cache[0]/2 - grad_h_cache[2]/2;
grad_v_cache0 [2] <= grad_v_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [2] + 1) : (grad_v_cache [2]); channel_cache_correct0[1] <= channel_cache_correct[1] - grad_v_cache[0]/2 - grad_v_cache[2]/2;
grad_45_cache0 [0] <= grad_45_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [0] + 1) : (grad_45_cache [0]); channel_cache_correct0[2] <= channel_cache_correct[2] - grad_i_cache[0]/2 - grad_i_cache[2]/2;
grad_45_cache0 [1] <= grad_45_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [1] + 1) : (grad_45_cache [1]); channel_cache_correct0[3] <= channel_cache_correct[3] - grad_t_cache[0]/2 - grad_t_cache[2]/2;
grad_45_cache0 [2] <= grad_45_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [2] + 1) : (grad_45_cache [2]);
grad_135_cache0[0] <= grad_135_cache[0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[0] + 1) : (grad_135_cache[0]);
grad_135_cache0[1] <= grad_135_cache[1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[1] + 1) : (grad_135_cache[1]);
grad_135_cache0[2] <= grad_135_cache[2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[2] + 1) : (grad_135_cache[2]);
channel_cache_correct0[0] <= channel_cache_correct[0] + grad_h_cache[0]/4 + grad_h_cache[2]/4;
channel_cache_correct0[1] <= channel_cache_correct[1] + grad_v_cache[0]/4 + grad_v_cache[2]/4;
channel_cache_correct0[2] <= channel_cache_correct[2] + grad_45_cache[0]/4 + grad_45_cache[2]/4;
channel_cache_correct0[3] <= channel_cache_correct[3] + grad_135_cache[0]/4 + grad_135_cache[2]/4;
end end
if(pipeline_valid[4]) begin //计算中位数 if(pipeline_valid[4]) begin //计算中位数
pipeline_user[5] <= pipeline_user[4];
channel_cache2 <= channel_cache1; channel_cache2 <= channel_cache1;
for (i = 0; i < 4; i = i + 1) channel_cache_correct1[i] <= channel_cache_correct0[i]; for(i=0;i<4;i=i+1) channel_cache_correct1[i] <= (channel_cache_correct0[i] < 0) ? (0) : (channel_cache_correct0[i]);
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_h_cache1[i] <= grad_h_cache0[i]; // for(i=0;i<4;i=i+1) channel_cache_correct1[i] <= channel_cache_correct0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_v_cache1[i] <= grad_v_cache0[i]; for(i=0;i<3;i=i+1) grad_h_cache1[i] <= grad_h_cache0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_45_cache1[i] <= grad_45_cache0[i]; for(i=0;i<3;i=i+1) grad_v_cache1[i] <= grad_v_cache0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_135_cache1[i] <= grad_135_cache0[i]; for(i=0;i<3;i=i+1) grad_i_cache1[i] <= grad_i_cache0[i];
for(i=0;i<3;i=i+1) grad_t_cache1[i] <= grad_t_cache0[i];
grad_median_cache[0] <= MEDIAN(grad_h_cache0); grad_median_cache[0] <= MEDIAN(grad_h_cache0);
grad_median_cache[1] <= MEDIAN(grad_v_cache0); grad_median_cache[1] <= MEDIAN(grad_v_cache0);
grad_median_cache[2] <= MEDIAN(grad_45_cache0); grad_median_cache[2] <= MEDIAN(grad_i_cache0);
grad_median_cache[3] <= MEDIAN(grad_135_cache0); grad_median_cache[3] <= MEDIAN(grad_t_cache0);
end end
if(pipeline_valid[5]) begin //计算最小值，判断最小梯度方向 if(pipeline_valid[5]) begin //计算最小值，判断最小梯度方向
pipeline_user[6] <= pipeline_user[5];
channel_cache3 <= channel_cache2; channel_cache3 <= channel_cache2;
for(i=0;i<4;i=i+1) channel_cache_correct2[i] <= channel_cache_correct1[i]; for(i=0;i<4;i=i+1) channel_cache_correct2[i] <= channel_cache_correct1[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_h_cache2[i] <= grad_h_cache1[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_v_cache2[i] <= grad_v_cache1[i]; grad_cache_center[0] <= grad_h_cache1[1]/4;
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_45_cache2[i] <= grad_45_cache1[i]; grad_cache_center[1] <= grad_v_cache1[1]/4;
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_135_cache2[i] <= grad_135_cache1[i]; grad_cache_center[2] <= grad_i_cache1[1]/4;
grad_cache_center[3] <= grad_t_cache1[1]/4;
grad_cache_excute[0] <= grad_h_cache1[0] + grad_h_cache1[2] + THRESHOLD;
grad_cache_excute[1] <= grad_v_cache1[0] + grad_v_cache1[2] + THRESHOLD;
grad_cache_excute[2] <= grad_i_cache1[0] + grad_i_cache1[2] + THRESHOLD;
grad_cache_excute[3] <= grad_t_cache1[0] + grad_t_cache1[2] + THRESHOLD;
flag_which_dict <= MIN(grad_median_cache); flag_which_dict <= MIN(grad_median_cache);
end end
if(pipeline_valid[6]) begin //在最小梯度方向上判断中心点是否是坏点 if(pipeline_valid[6]) begin //在最小梯度方向上判断中心点是否是坏点
pipeline_user[7] <= pipeline_user[6];
dic2 <= flag_which_dict;
channel_cache4 <= channel_cache3; channel_cache4 <= channel_cache3;
channel_cache_correct_final <= channel_cache_correct2[flag_which_dict]; channel_cache_correct_final <= channel_cache_correct2[flag_which_dict][DATA_WIDTH-1:0];
case (flag_which_dict) case (flag_which_dict)
2'b00: 2'b00, 2'b01: flag_if_need_corection <= (grad_cache_center[flag_which_dict] > grad_cache_excute[flag_which_dict]);
flag_if_need_corection <= grad_h_cache2[1] / 4 > (grad_h_cache2[0] + grad_h_cache2[2]); 2'b10, 2'b11: flag_if_need_corection <= (grad_cache_center[2] > grad_cache_excute[2]) && ((grad_cache_center[3] > grad_cache_excute[3]));
2'b01:
flag_if_need_corection <= grad_v_cache2[1] / 4 > (grad_v_cache2[0] + grad_v_cache2[2]);
2'b10:
flag_if_need_corection <= grad_45_cache2[1] / 4 > (grad_45_cache2[0] + grad_45_cache2[2]);
2'b11:
flag_if_need_corection <= grad_135_cache2[1]/4 > (grad_135_cache2[0] + grad_135_cache2[2]);
endcase endcase
end end
if(pipeline_valid[7]) begin //如果是坏点，输出计算后的值；如果不是坏点，输出原值 if(pipeline_valid[7]) begin //如果是坏点，输出计算后的值；如果不是坏点，输出原值
if (MODULE_ENABLE) // if(flag_if_need_corection == 1'b1 && channel_cache_correct_final == 0) $stop;
out_data <= (flag_if_need_corection)?((LABLE_ENABLE)?(12'hFFF):(channel_cache_correct_final)):(channel_cache4); pipeline_user[8] <= pipeline_user[7];
else out_data <= channel_cache4; if(MODULE_ENABLE) begin
case(LABLE_ENABLE)
0: out_data <= (flag_if_need_corection)?(channel_cache_correct_final):(channel_cache4);
1: out_data <= (flag_if_need_corection)?(12'hFFF):(channel_cache4);
2: begin
case(dic2)
2'b00: out_data <= (12'h00F);
2'b01: out_data <= (12'h0F0);
2'b10: out_data <= (12'hF00);
2'b11: out_data <= (12'h0FF);
endcase
end
endcase
end else out_data <= channel_cache4;
end end
end end
end end
function [DATA_WIDTH-1+EXPAND_BITS:0] MEDIAN; function signed [DATA_WIDTH-1+EXPAND_BITS:0] MEDIAN;
input [DATA_WIDTH-1+EXPAND_BITS:0] inx[3]; input signed [DATA_WIDTH-1+EXPAND_BITS:0] inx[3];
begin begin
if ((inx[0] >= inx[1] && inx[1] >= inx[2]) || (inx[2] >= inx[1] && inx[1] >= inx[0])) if((inx[0] >= inx[1] && inx[1] >= inx[2]) || (inx[2] >= inx[1] && inx[1] >= inx[0])) MEDIAN = inx[1];
MEDIAN = inx[1]; else if((inx[1] >= inx[0] && inx[0] >= inx[2]) || (inx[2] >= inx[0] && inx[0] >= inx[1])) MEDIAN = inx[0];
else if ((inx[1] >= inx[0]) || (inx[0] >= inx[1])) MEDIAN = inx[0];
else MEDIAN = inx[2]; else MEDIAN = inx[2];
end end
endfunction endfunction
function [1:0] MIN; function [1:0] MIN;
input [DATA_WIDTH-1+EXPAND_BITS:0] inx[4]; input signed [DATA_WIDTH-1+EXPAND_BITS:0] inx[4];
begin begin
if (inx[0] >= inx[1] && inx[0] >= inx[2] && inx[0] >= inx[3]) MIN = 2'b00; if(inx[0] <= inx[1] && inx[0] <= inx[2] && inx[0] <= inx[3]) MIN = 2'b00;
else if (inx[1] >= inx[0] && inx[1] >= inx[2] && inx[1] >= inx[3]) MIN = 2'b01; else if(inx[1] <= inx[2] && inx[1] <= inx[3]) MIN = 2'b01;
else if (inx[2] >= inx[0] && inx[2] >= inx[1] && inx[2] >= inx[3]) MIN = 2'b10; else if(inx[2] <= inx[3]) MIN = 2'b10;
else MIN = 2'b11; else MIN = 2'b11;
end end
endfunction endfunction
@ -299,4 +303,3 @@ module DPC #(
endmodule endmodule

1
rtl/BayerProcess/Demosaic2.sv
View File

@ -1,4 +1,3 @@
`timescale 1ns/1ps
module Demosaic2 #( module Demosaic2 #(
parameter reg [15:0] IM_WIDTH = 512, // 图像宽度 parameter reg [15:0] IM_WIDTH = 512, // 图像宽度
parameter reg [15:0] IM_HEIGHT = 256, // 图像高度 parameter reg [15:0] IM_HEIGHT = 256, // 图像高度

111
rtl/BayerProcess/Demosaic_Pipeline.sv
View File

@ -1,8 +1,5 @@
`timescale 1ns / 1ps
module Demosaic_Pipeline #( module Demosaic_Pipeline #(
parameter WINDOW_LENGTH = 3, parameter WINDOW_LENGTH = 3,
parameter reg [15:0] TOTAL_WIDTH = 512 + 3, // 总图像宽度
parameter reg [15:0] TOTAL_HEIGHT = 256 + 3, // 总图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值 parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽 parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
)( )(
@ -10,22 +7,22 @@ module Demosaic_Pipeline #(
input wire reset, input wire reset,
input wire [DATA_WIDTH - 1:0] in_data [WINDOW_LENGTH*WINDOW_LENGTH], // 数据输入线.第一列数据在[0],[1],[2]中 input wire [DATA_WIDTH - 1:0] in_data [WINDOW_LENGTH*WINDOW_LENGTH], // 数据输入线.第一列数据在[0],[1],[2]中
input wire [7:0] in_user,
output reg [DATA_WIDTH - 1:0] out_data [3], // 数据输出线，3、2、1分别表示r、g、b output reg [DATA_WIDTH - 1:0] out_data [3], // 数据输出线，3、2、1分别表示r、g、b
output wire [7:0] out_user,
input wire in_valid, input wire in_valid,
output wire out_valid, output wire out_valid,
input wire in_ready, input wire in_ready,
output wire out_ready, output wire out_ready
output reg out_hsync, // 行同步，一行第一个像素点输出的同时高电平
output reg out_fsync // 帧同步，一帧第一个像素点输出的同时高电平
); );
localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH; localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH;
localparam PIPILINE = 4; localparam PIPILINE = 2;
reg [PIPILINE-1:0] pipeline_valid; reg [PIPILINE-1:0] pipeline_valid;
reg [7:0] pipeline_user[PIPILINE];
wire pipeline_running; wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1]; assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
@ -33,89 +30,71 @@ module Demosaic_Pipeline #(
assign out_ready = pipeline_running; assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高 //out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = pipeline_valid[PIPILINE-1]; assign out_valid = pipeline_valid[PIPILINE-1];
assign out_user = pipeline_user[PIPILINE-1];
reg [DATA_WIDTH-1:0] data_cache [DATA_NUM]; // 缓存颜色数据，行列nxn reg pos_x, pos_y;
reg [DATA_WIDTH-1:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [31:0] pos_x, pos_y, temp_pos_x1, temp_pos_y1, temp_pos_x2, temp_pos_y2;
reg [DATA_WIDTH-1:0] red, blue, green; reg [DATA_WIDTH-1:0] red, blue, green;
reg [DATA_WIDTH-1:0] red_cache[4], blue_cache[4], green_cache[4];
reg [1:0] raw_type; reg [1:0] raw_type;
integer i; integer i;
always @(posedge clk) begin always @(posedge clk) begin
if(reset) begin if(reset) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= 0; for(i=0;i<4;i=i+1) red_cache[i] <= 0;
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= 0; for(i=0;i<4;i=i+1) blue_cache[i] <= 0;
for(i=0;i<4;i=i+1) green_cache[i] <= 0;
pipeline_valid <= 0; pipeline_valid <= 0;
{red, green, blue} <= 0; {red, green, blue} <= 0;
{out_data[2],out_data[1],out_data[0]} <= 0; {out_data[2],out_data[1],out_data[0]} <= 0;
{out_hsync, out_fsync} <= 0; for(i=0;i<PIPILINE;i=i+1) pipeline_user[i] <= 0;
pos_x <= ~0; pos_x <= 0;
pos_y <= ~0; pos_y <= 0;
temp_pos_x1 <= ~0;
temp_pos_y1 <= ~0;
temp_pos_x2 <= ~0;
temp_pos_y2 <= ~0;
raw_type <= RAW_TYPE;
end else if(pipeline_running) begin end else if(pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid}; pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if(in_valid) begin if(in_valid) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= in_data[i]; pipeline_user[0] <= in_user;
pos_x <= (pos_x >= TOTAL_WIDTH - 1) ? (0) : (pos_x + 1); pos_x <= (in_user[0])?(0):(~pos_x);
pos_y <= (pos_x >= TOTAL_WIDTH - 1)?((pos_y >= TOTAL_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y); pos_y <= (in_user[0])?((in_user[1])?(0):(~pos_y)):(pos_y);
red_cache[0] <= (in_data[3] >> 1) + (in_data[5] >> 1);
red_cache[1] <= (in_data[0] >> 2) + (in_data[2] >> 2) + (in_data[6] >> 2) + (in_data[8] >> 2);
red_cache[2] <= in_data[4];
red_cache[3] <= (in_data[1] >> 1) + (in_data[7] >> 1);
green_cache[0] <= in_data[4];
green_cache[1] <= (in_data[1] >> 2) + (in_data[3] >> 2) + (in_data[5] >> 2) + (in_data[7] >> 2);
green_cache[2] <= (in_data[1] >> 2) + (in_data[3] >> 2) + (in_data[5] >> 2) + (in_data[7] >> 2);
green_cache[3] <= in_data[4];
blue_cache[0] <= (in_data[1] >> 1) + (in_data[7] >> 1);
blue_cache[1] <= in_data[4];
blue_cache[2] <= (in_data[0] >> 2) + (in_data[2] >> 2) + (in_data[6] >> 2) + (in_data[8] >> 2);
blue_cache[3] <= (in_data[3] >> 1) + (in_data[5] >> 1);
end end
if(pipeline_valid[0]) begin if(pipeline_valid[0]) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= data_cache0[i]; pipeline_user[1] <= pipeline_user[0];
temp_pos_x1 <= pos_x; out_data[2] <= red_cache[raw_type];
temp_pos_y1 <= pos_y; out_data[1] <= green_cache[raw_type];
case (RAW_TYPE) out_data[0] <= blue_cache[raw_type];
2'b00: raw_type <= {pos_y[0], pos_x[0]};
2'b01: raw_type <= {pos_y[0], ~pos_x[0]};
2'b10: raw_type <= {~pos_y[0], pos_x[0]};
2'b11: raw_type <= {~pos_y[0], ~pos_x[0]};
endcase
end end
if (pipeline_valid[1]) begin
temp_pos_x2 <= temp_pos_x1;
temp_pos_y2 <= temp_pos_y1;
case (raw_type)
0: begin // Missing B, R on G
blue <= (data_cache[1] >> 1) + (data_cache[7] >> 1);
red <= (data_cache[3] >> 1) + (data_cache[5] >> 1);
green <= data_cache[4];
end
1: begin // Missing G, R on B
green <= (data_cache[1] >> 2) + (data_cache[3] >> 2) + (data_cache[5] >> 2) + (data_cache[7] >> 2);
red <= (data_cache[0] >> 2) + (data_cache[2] >> 2) + (data_cache[6] >> 2) + (data_cache[8] >> 2);
blue <= data_cache[4];
end
2: begin // Missing G, B on R
green <= (data_cache[1] >> 2) + (data_cache[3] >> 2) + (data_cache[5] >> 2) + (data_cache[7] >> 2);
blue <= (data_cache[0] >> 2) + (data_cache[2] >> 2) + (data_cache[6] >> 2) + (data_cache[8] >> 2);
red <= data_cache[4];
end
3: begin // Missing B, R on G
red <= (data_cache[1] >> 1) + (data_cache[7] >> 1);
blue <= (data_cache[3] >> 1) + (data_cache[5] >> 1);
green <= data_cache[4];
end
endcase
end
if (pipeline_valid[2]) begin
{out_data[2], out_data[1], out_data[0]} <= {red, green, blue};
out_hsync <= (temp_pos_x2 == 0);
out_fsync <= ((temp_pos_x2 == 0) && (temp_pos_y2 == 0));
end
end end
end end
// 0:grg 1:rgr 2:bgb 3:gbg 036 窗口右移，0<->1 2<->3; 窗口下移，0<->2，1<->3。 // 0:grg 1:rgr 2:bgb 3:gbg 036 窗口右移，0<->1 2<->3; 窗口下移，0<->2，1<->3。
// bgb gbg grg rgr 147 // bgb gbg grg rgr 147
// grg rgr bgb gbg 258 // grg rgr bgb gbg 258
always @(*) begin
case (RAW_TYPE)
2'b00: raw_type = { pos_y, pos_x};
2'b01: raw_type = { pos_y, ~pos_x};
2'b10: raw_type = {~pos_y, pos_x};
2'b11: raw_type = {~pos_y, ~pos_x};
endcase
end
endmodule endmodule

1
rtl/BayerProcess/Gowin_SDPB.sv
View File

@ -1,5 +1,4 @@
//Gowin SDPB IP<49>˷<EFBFBD><CBB7><EFBFBD><EFBFBD>ļ<EFBFBD> //Gowin SDPB IP<49>˷<EFBFBD><CBB7><EFBFBD><EFBFBD>ļ<EFBFBD>
`timescale 1ns / 1ps
module Gowin_SDPB ( module Gowin_SDPB (
input wire clka, input wire clka,
input wire clkb, //no use input wire clkb, //no use

56
rtl/BayerProcess/SHIFT_REGISTER.sv
View File

@ -1,9 +1,7 @@
//RAM-BASED移位寄存器 //RAM-BASED移位寄存器
`timescale 1ns / 1ps
module SHIFT_REGISTER #( module SHIFT_REGISTER #(
parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽 parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
parameter IMAGE_WIDTH = 1936, //MAX 2048
parameter IFOUTIMME = 1'b0 //此项为0时，直至RAM存满IMAGE_WIDTH后再输出valid，为1时立即输出valid，无论是否存满 parameter IFOUTIMME = 1'b0 //此项为0时，直至RAM存满IMAGE_WIDTH后再输出valid，为1时立即输出valid，无论是否存满
)( )(
// 基本信号 // 基本信号
@ -11,7 +9,9 @@ module SHIFT_REGISTER #(
input wire reset, input wire reset,
// 数据线 // 数据线
input wire [DATA_WIDTH - 1:0] in_data, input wire [DATA_WIDTH - 1:0] in_data,
input wire [7:0] in_user, //in_user[0]是hstart, 行开始标志位, 用于给SHIFT_REGISTER判断输出与输入data的addr距离
output wire [DATA_WIDTH - 1:0] out_data, output wire [DATA_WIDTH - 1:0] out_data,
output wire [7:0] out_user,
// 有效信号 // 有效信号
input wire in_valid, // 上一模块输出数据有效 input wire in_valid, // 上一模块输出数据有效
output wire out_valid // 当前模块输出数据有效 output wire out_valid // 当前模块输出数据有效
@ -29,26 +29,39 @@ module SHIFT_REGISTER #(
assign ceb = in_valid_temp0; assign ceb = in_valid_temp0;
assign out_valid = in_valid_temp1; assign out_valid = in_valid_temp1;
always @(posedge clk) begin wire hstart;
if (reset) fulldone <= 0; assign hstart = in_user[0];
else if (addr_b == IMAGE_WIDTH - 1) fulldone <= 1; reg [15:0] wr_rd_distance_cnt;
else fulldone <= fulldone;
end
always @(posedge clk) begin always @(posedge clk) begin
if(reset) begin if(reset) begin
addr_a <= IMAGE_WIDTH + 1; addr_a <= ~0;
addr_b <= 0; addr_b <= 0;
wr_rd_distance_cnt <= 0;
end else if(cea) begin end else if(cea) begin
addr_a <= addr_a + 1; addr_a <= addr_a + 1;
if(hstart) begin
wr_rd_distance_cnt <= 0;
addr_b <= addr_a + 1 - (wr_rd_distance_cnt + 2);
end else begin
addr_b <= addr_b + 1; addr_b <= addr_b + 1;
wr_rd_distance_cnt <= wr_rd_distance_cnt + 1;
end
end else begin end else begin
addr_a <= addr_a; addr_a <= addr_a;
addr_b <= addr_b; addr_b <= addr_b;
wr_rd_distance_cnt <= wr_rd_distance_cnt;
end end
end end
always @(posedge clk) begin
if(reset) fulldone <= 0;
else if(cea && hstart && (addr_b != 0)) fulldone <= 1;
else fulldone <= fulldone;
end
wire [15:0] din, dout;
assign din = {{(16-DATA_WIDTH){1'b0}},in_data};
assign out_data = dout[DATA_WIDTH-1:0];
// Single-Double-Port-BRAM-IP Bypass Normal // Single-Double-Port-BRAM-IP Bypass Normal
Gowin_SDPB Gowin_SDPB_inst( Gowin_SDPB Gowin_SDPB_inst(
.clka(clk), //input clka .clka(clk), //input clka
@ -61,12 +74,29 @@ module SHIFT_REGISTER #(
.ada(addr_a), //input [10:0] ada .ada(addr_a), //input [10:0] ada
.adb(addr_b), //input [10:0] adb .adb(addr_b), //input [10:0] adb
.din (in_data), //input [15:0] din .din(din), //input [15:0] din
.dout(out_data), //output [15:0] dout .dout(dout), //output [15:0] dout
.oce(1) //input oce
);
// Single-Double-Port-BRAM-IP Bypass Normal
Gowin_SDPB_USER Gowin_SDPB_user_inst(
.clka(clk), //input clka
.clkb(clk), //input clkb
.reset(reset), //input reset
.cea(cea), //input cea
.ceb(ceb), //input ceb
.ada(addr_a), //input [10:0] ada
.adb(addr_b), //input [10:0] adb
.din(in_user), //input [7:0] din
.dout(out_user), //output [7:0] dout
.oce(1) //input oce .oce(1) //input oce
); );
endmodule endmodule

93
rtl/BayerProcess/Windows.sv
View File

@ -1,22 +1,21 @@
`timescale 1ns / 1ps
module Windows #( module Windows #(
parameter DATA_WIDTH = 16, parameter DATA_WIDTH = 16,
parameter IMAGE_WIDTH = 1936,
parameter IMAGE_HEIGHT = 1088,
parameter WINDOWS_WIDTH = 3, parameter WINDOWS_WIDTH = 3,
parameter WINDOWS_ANCHOR_X = 1, //禁止大于WINDOWS_WIDTH-1 parameter WINDOWS_ANCHOR_X = 1,//禁止大于WINDOWS_WIDTH-1
parameter WINDOWS_ANCHOR_Y = 1 //禁止大于WINDOWS_WIDTH-1 parameter WINDOWS_ANCHOR_Y = 1 //禁止大于WINDOWS_WIDTH-1
)( )(
// 基本信号 // 基本信号
input wire clk, input wire clk,
input wire reset, input wire reset,
// 数据线 // 数据线
input wire [DATA_WIDTH - 1:0] in_data, input wire [DATA_WIDTH - 1:0] in_data,
output reg [DATA_WIDTH - 1:0] out_data[WINDOWS_WIDTH*WINDOWS_WIDTH], // 数据输出线 input wire [7:0] in_user,
// 有效信号 output reg [DATA_WIDTH - 1:0] out_data [WINDOWS_WIDTH*WINDOWS_WIDTH], // 数据输出线
input wire in_valid, // 上一模块输出数据有效 output wire [7:0] out_user,
output reg out_valid, // 当前模块输出数据有效 // 有效信号
// 准备信号 Windows模块无法停止，因此默认不处理准备信号 input wire in_valid, // 上一模块输出数据有效
output wire out_valid, // 当前模块输出数据有效
// 准备信号 Windows模块无法停止，因此默认不处理准备信号
input wire in_ready, input wire in_ready,
output wire out_ready output wire out_ready
); );
@ -24,11 +23,17 @@ module Windows #(
assign out_ready = 1'b1; assign out_ready = 1'b1;
reg [DATA_WIDTH - 1:0] regx_in_data[WINDOWS_WIDTH-1]; reg [DATA_WIDTH - 1:0] regx_in_data[WINDOWS_WIDTH-1];
reg [DATA_WIDTH - 1:0] regx_out_data[WINDOWS_WIDTH-1]; wire [DATA_WIDTH - 1:0] regx_out_data[WINDOWS_WIDTH-1];
reg [WINDOWS_WIDTH - 2:0] regx_in_valid, regx_out_valid; reg [7:0] regx_in_user[WINDOWS_WIDTH-1];
wire [7:0] regx_out_user[WINDOWS_WIDTH-1];
reg [WINDOWS_WIDTH - 2:0] regx_in_valid;
wire [WINDOWS_WIDTH - 2:0] regx_out_valid;
reg [DATA_WIDTH - 1:0] data_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)]; reg [DATA_WIDTH - 1:0] data_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)];
reg [7:0] user_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)];
reg [7:0] out_user_windows[WINDOWS_WIDTH*WINDOWS_WIDTH];
assign out_user = out_user_windows[(WINDOWS_WIDTH*WINDOWS_ANCHOR_Y) + WINDOWS_ANCHOR_X];
/* outdata[x]: /* outdata[x]:
SHIFT_REG1 -> 0 3 6 . . SHIFT_REG1 -> 0 3 6 . .
@ -38,57 +43,62 @@ SHIFT_REG0 -> 1 4 7 . .
. . . . . .
*/ */
reg out_valid_output;
reg firstframedone; reg firstframedone;
reg [15:0] pos_x, pos_y;
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if(reset) firstframedone <= 0;
pos_x <= 0; else if(out_user == 1'b1) firstframedone <= 1;
pos_y <= 0; else firstframedone <= firstframedone;
firstframedone <= 0;
end else if (regx_out_valid[WINDOWS_WIDTH-2]) begin
pos_x <= (pos_x >= IMAGE_WIDTH - 1) ? (0) : (pos_x + 1);
pos_y <= (pos_x >= IMAGE_WIDTH - 1)?((pos_y >= IMAGE_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
firstframedone <= (pos_x >= IMAGE_WIDTH - 1 && pos_y >= IMAGE_HEIGHT - 1)?(1):(firstframedone);
end else begin
pos_x <= pos_x;
pos_y <= pos_y;
firstframedone <= firstframedone;
end end
always @(posedge clk) begin
if(reset) out_valid_output <= 0;
else out_valid_output <= regx_out_valid[WINDOWS_WIDTH-2];
end end
assign out_valid = out_valid_output & (firstframedone || out_user);
integer i,j; integer i,j;
always @(posedge clk) begin always @(posedge clk) begin
if(reset)begin if(reset)begin
for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH;i=i+1) out_data[i] <= 0; for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH;i=i+1) out_data[i] <= 0;
out_valid <= 0; for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH;i=i+1) out_user_windows[i] <= 0;
end else if(regx_out_valid[WINDOWS_WIDTH-2])begin end else if(regx_out_valid[WINDOWS_WIDTH-2])begin
for(i=0;i<WINDOWS_WIDTH;i=i+1) begin for(i=0;i<WINDOWS_WIDTH;i=i+1) begin
for(j=0;j<WINDOWS_WIDTH;j=j+1) begin for(j=0;j<WINDOWS_WIDTH;j=j+1) begin
if(i==WINDOWS_WIDTH-1) begin if(i==WINDOWS_WIDTH-1) begin
if(j==0) out_data[(WINDOWS_WIDTH*i)+j] <= regx_out_data[WINDOWS_WIDTH-2]; if(j==0) out_data[(WINDOWS_WIDTH*i)+j] <= regx_out_data[WINDOWS_WIDTH-2];
else out_data[(WINDOWS_WIDTH*i)+j] <= data_out_shift[j-1][2*j-1]; else out_data[(WINDOWS_WIDTH*i)+j] <= data_out_shift[j-1][2*j-1];
end else out_data[(WINDOWS_WIDTH*i)+j] <= out_data[(WINDOWS_WIDTH*(i+1))+j]; end
else out_data[(WINDOWS_WIDTH*i)+j] <= out_data[(WINDOWS_WIDTH*(i+1))+j];
end
end
for(i=0;i<WINDOWS_WIDTH;i=i+1) begin
for(j=0;j<WINDOWS_WIDTH;j=j+1) begin
if(i==WINDOWS_WIDTH-1) begin
if(j==0) out_user_windows[(WINDOWS_WIDTH*i)+j] <= regx_out_user[WINDOWS_WIDTH-2];
else out_user_windows[(WINDOWS_WIDTH*i)+j] <= user_out_shift[j-1][2*j-1];
end
else out_user_windows[(WINDOWS_WIDTH*i)+j] <= out_user_windows[(WINDOWS_WIDTH*(i+1))+j];
end end
end end
if (firstframedone) out_valid <= 1;
else
out_valid <= ~((pos_y <= WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1 && pos_x < WINDOWS_WIDTH-WINDOWS_ANCHOR_X-1) || (pos_y < WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1));
end else begin end else begin
for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH-1;i=i+1) out_data[i] <= out_data[i]; for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH-1;i=i+1) out_data[i] <= out_data[i];
out_valid <= 0; for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH-1;i=i+1) out_user_windows[i] <= out_user_windows[i];
end end
end end
always @(posedge clk) begin always @(posedge clk) begin
if (reset) if(reset) for(i=0;i<WINDOWS_WIDTH-1;i=i+1) for(j=0;j<WINDOWS_WIDTH-1;j=j+1) begin
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) data_out_shift[i][j] <= 0;
for (j = 0; j < WINDOWS_WIDTH - 1; j = j + 1) data_out_shift[i][j] <= 0; user_out_shift[i][j] <= 0;
else end else for(i=0;i<WINDOWS_WIDTH-1;i=i+1) begin
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
for(j=0;j<2*(WINDOWS_WIDTH-1);j=j+1) begin for(j=0;j<2*(WINDOWS_WIDTH-1);j=j+1) begin
if(i==WINDOWS_WIDTH-2 && j==0) data_out_shift[i][j] <= in_data; if(i==WINDOWS_WIDTH-2 && j==0) data_out_shift[i][j] <= in_data;
else if(j==0) data_out_shift[i][j] <= regx_out_data[(WINDOWS_WIDTH-2-i)-1]; else if(j==0) data_out_shift[i][j] <= regx_out_data[(WINDOWS_WIDTH-2-i)-1];
else data_out_shift[i][j] <= data_out_shift[i][j-1]; else data_out_shift[i][j] <= data_out_shift[i][j-1];
if(i==WINDOWS_WIDTH-2 && j==0) user_out_shift[i][j] <= in_user;
else if(j==0) user_out_shift[i][j] <= regx_out_user[(WINDOWS_WIDTH-2-i)-1];
else user_out_shift[i][j] <= user_out_shift[i][j-1];
end end
end end
end end
@ -98,6 +108,10 @@ SHIFT_REG0 -> 1 4 7 . .
if(i == 0) regx_in_data[i] = in_data; if(i == 0) regx_in_data[i] = in_data;
else regx_in_data[i] = regx_out_data[i-1]; else regx_in_data[i] = regx_out_data[i-1];
end end
for(i=0;i<WINDOWS_WIDTH-1;i=i+1)begin
if(i == 0) regx_in_user[i] = in_user;
else regx_in_user[i] = regx_out_user[i-1];
end
for(i=0;i<WINDOWS_WIDTH-1;i=i+1)begin for(i=0;i<WINDOWS_WIDTH-1;i=i+1)begin
if(i == 0) regx_in_valid[i] = in_valid; if(i == 0) regx_in_valid[i] = in_valid;
else regx_in_valid[i] = regx_out_valid[i-1]; else regx_in_valid[i] = regx_out_valid[i-1];
@ -109,13 +123,14 @@ SHIFT_REG0 -> 1 4 7 . .
for(o = 0; o < WINDOWS_WIDTH - 1; o = o + 1'b1) begin:shift_register for(o = 0; o < WINDOWS_WIDTH - 1; o = o + 1'b1) begin:shift_register
SHIFT_REGISTER #( SHIFT_REGISTER #(
.DATA_WIDTH(DATA_WIDTH), .DATA_WIDTH(DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH),
.IFOUTIMME(1'b1) .IFOUTIMME(1'b1)
)shift_registerx( )shift_registerx(
.clk (clk), .clk (clk),
.reset (reset), .reset (reset),
.in_data (regx_in_data[o]), .in_data (regx_in_data[o]),
.in_user (regx_in_user[o]),
.out_data (regx_out_data[o]), .out_data (regx_out_data[o]),
.out_user (regx_out_user[o]),
.in_valid (regx_in_valid[o]), .in_valid (regx_in_valid[o]),
.out_valid(regx_out_valid[o]) .out_valid(regx_out_valid[o])
); );

86
rtl/BayerProcess/Windows_tb.sv Normal file
View File

@ -0,0 +1,86 @@
`default_nettype none
module Windows_tb ();
// Related Paras
parameter int CLK_PERIOD = 20;
parameter int DATA_WIDTH = 16;
parameter int WINDOWS_WIDTH = 5;
parameter int DATA_LENGTH = 100;
parameter int DATA_HEIGHT = 100;
parameter int DATA_FLAMES = 3;
// Related Ports
bit clk = 1;
bit rst = 0;
logic in_valid = 0;
logic [DATA_WIDTH - 1:0] in_data = 0;
logic [7:0] in_user = 0;
logic out_valid = 0;
logic [DATA_WIDTH - 1:0] out_data[WINDOWS_WIDTH ** 2] = '{default: 0};
logic [7:0] out_user = 0;
logic in_ready = 0;
logic out_ready = 0;
// Generate Clk
always #(CLK_PERIOD / 2) clk = ~clk;
// Reset Module
initial begin
rst = 1;
#(10 * CLK_PERIOD);
rst = 0;
end
// Send Data
initial begin
#(12 * CLK_PERIOD);
in_ready = 1;
#(3 * CLK_PERIOD);
for (int f = 0; f < DATA_FLAMES; ++f) begin
for (int j = 0; j < DATA_HEIGHT; ++j) begin
for (int i = 0; i < DATA_LENGTH; ++i) begin
in_user[1] = (j == 0 && i == 0) ? 1'b1 : 1'b0;
in_user[0] = (i == 0) ? 1'b1 : 1'b0;
in_data = j * DATA_LENGTH + i;
in_valid = 1;
#CLK_PERIOD;
end
end
in_valid = 0;
in_user = 0;
#(50 * CLK_PERIOD);
end
$finish(100 * CLK_PERIOD);
end
// Connect to modules
GSR GSR (.GSRI(1'b1));
Windows #(
.DATA_WIDTH (DATA_WIDTH),
.WINDOWS_WIDTH (WINDOWS_WIDTH),
.WINDOWS_ANCHOR_X(2),
.WINDOWS_ANCHOR_Y(2)
) Windows_inst (
.clk (clk),
.reset(rst),
.in_valid(in_valid),
.in_data (in_data),
.in_user (in_user),
.out_valid(out_valid),
.out_data (out_data),
.out_user (out_user),
.in_ready (in_ready),
.out_ready(out_ready)
);
endmodule

121
rtl/BayerProcess/fifo_isp_adapter.sv Normal file
View File

@ -0,0 +1,121 @@
module fifo_isp_adapter #(
parameter DATA_WIDTH = 16
) (
input wire reset,
input wire camera_clk,
input wire in_valid,
input wire [DATA_WIDTH - 1:0] in_data,
input wire in_fsync,
input wire in_hsync,
input wire isp_clk,
output reg out_valid,
output reg [DATA_WIDTH - 1:0] out_data,
output reg [7:0] out_user
);
localparam GIVEUP_FRAME = 1;
reg [5:0] frame_count;
wire flag_frame_init_done;
// assign flag_frame_init_done = (frame_count >= GIVEUP_FRAME);
assign flag_frame_init_done = 1;
reg in_valid_d0, in_fsync_d0, in_hsync_d0;
wire in_fsync_pos, in_hsync_pos;
assign in_fsync_pos = in_fsync && !in_fsync_d0;
assign in_hsync_pos = in_hsync && !in_hsync_d0;
always @(posedge camera_clk) begin
if (reset) in_fsync_d0 <= 0;
else in_fsync_d0 <= in_fsync;
end
always @(posedge camera_clk) begin
if (reset) in_hsync_d0 <= 0;
else in_hsync_d0 <= in_hsync;
end
always @(posedge camera_clk) begin
if (reset) frame_count <= 0;
else if (in_fsync_pos && frame_count <= GIVEUP_FRAME - 1) frame_count <= frame_count + 1;
else frame_count <= frame_count;
end
reg fstart, hstart;
reg fifo_in_valid;
reg [DATA_WIDTH-1:0] in_data_d0;
reg [23:0] fifo_in_data;
always @(posedge camera_clk) begin
if (reset) begin
hstart <= 0;
fstart <= 0;
fifo_in_valid <= 0;
fifo_in_data <= 0;
in_valid_d0 <= 0;
in_data_d0 <= 0;
end else begin
if (in_valid) in_data_d0 <= in_data;
else in_data_d0 <= in_data_d0;
in_valid_d0 <= in_valid;
if (in_fsync_pos) fstart <= 1;
else if (in_valid_d0 && flag_frame_init_done) fstart <= 0;
else fstart <= fstart;
if (in_hsync_pos) hstart <= 1;
else if (in_valid_d0 && flag_frame_init_done) hstart <= 0;
else hstart <= hstart;
if (in_valid_d0 && flag_frame_init_done) begin
fifo_in_valid <= 1;
fifo_in_data <= {{(24 - 1 - 1 - DATA_WIDTH) {1'b0}}, fstart, hstart, in_data_d0};
end else begin
fifo_in_valid <= 0;
fifo_in_data <= fifo_in_data;
end
end
end
reg fifo_rd_en;
wire real_fifo_rd_en;
wire fifo_empty;
wire [23:0] fifo_out_data;
assign real_fifo_rd_en = fifo_rd_en & (~fifo_empty);
always @(posedge isp_clk) begin
if (reset) fifo_rd_en <= 0;
else if (~fifo_empty) fifo_rd_en <= 1;
else fifo_rd_en <= 0;
end
always @(posedge isp_clk) begin
if (reset) begin
out_valid <= 0;
out_user <= 0;
out_data <= 0;
end else if (real_fifo_rd_en) begin
out_valid <= 1;
out_data <= fifo_out_data[DATA_WIDTH-1:0];
out_user <= {6'b0, fifo_out_data[DATA_WIDTH+1], fifo_out_data[DATA_WIDTH]};
end else begin
out_valid <= 0;
out_data <= out_data;
end
end
Camera2ISP_fifo Camera2ISP_fifo_u (
.Data(fifo_in_data), //input [23:0] Data
.Reset(reset),
.WrClk(camera_clk), //input WrClk
.RdClk(isp_clk), //input RdClk
.WrEn(fifo_in_valid), //input WrEn
.RdEn(real_fifo_rd_en), //input RdEn
.Q(fifo_out_data), //output [23:0] Q
.Empty(fifo_empty), //output Empty
.Full() //output Full
);
endmodule

51
rtl/BayerProcess/frame_size_detect.sv Normal file
View File

@ -0,0 +1,51 @@
module frame_size_detect (
input wire clk,
input wire reset,
input wire in_valid,
input wire hstart,
input wire fstart,
input wire [15:0] h_pixel,
input wire [15:0] v_pixel,
output wire h_pixel_correct,
output wire v_pixel_correct
);
reg [15:0] h_pixel_cnt, v_pixel_cnt;
reg [3:0] h_pixel_match_times, v_pixel_match_times;
assign h_pixel_correct = (h_pixel_match_times == 4'hF);
assign v_pixel_correct = (v_pixel_match_times == 4'hF);
always @(posedge clk) begin
if(reset) h_pixel_cnt <= 0;
else if(hstart & in_valid) h_pixel_cnt <= 0;
else if(in_valid) h_pixel_cnt <= h_pixel_cnt + 1;
else h_pixel_cnt <= h_pixel_cnt;
end
always @(posedge clk) begin
if(reset) h_pixel_match_times <= 0;
else if(hstart&in_valid) begin
if(h_pixel_cnt == h_pixel - 1) h_pixel_match_times <= (h_pixel_match_times == 4'hF)?(h_pixel_match_times):(h_pixel_match_times + 1);
else h_pixel_match_times <= 0;
end else h_pixel_match_times <= h_pixel_match_times;
end
always @(posedge clk) begin
if(reset) v_pixel_cnt <= 0;
else if(fstart & in_valid) v_pixel_cnt <= 0;
else if(hstart & in_valid) v_pixel_cnt <= v_pixel_cnt + 1;
else v_pixel_cnt <= v_pixel_cnt;
end
always @(posedge clk) begin
if(reset) v_pixel_match_times <= 0;
else if(fstart & in_valid) begin
if(v_pixel_cnt == v_pixel - 1) v_pixel_match_times <= (v_pixel_match_times == 4'hF)?(v_pixel_match_times):(v_pixel_match_times + 1);
else v_pixel_match_times <= 0;
end else v_pixel_match_times <= v_pixel_match_times;
end
endmodule

5
rtl/Color/ColorBlender.sv
View File

@ -1,4 +1,3 @@
`timescale 1ns/1ps
// 三通道图像合成一个RGB图像 // 三通道图像合成一个RGB图像
module ColorBlender #( module ColorBlender #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深 parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
@ -76,9 +75,9 @@ module ColorBlender #(
CALC_DATA: begin CALC_DATA: begin
if (enable) begin if (enable) begin
data_cal[0] <= (data_cal[0] * {16'b0, gain_red}) >> 16; data_cal[0] <= (data_cal[0] * {16'b0, gain_blue}) >> 16;
data_cal[1] <= (data_cal[1] * {16'b0, gain_green}) >> 16; data_cal[1] <= (data_cal[1] * {16'b0, gain_green}) >> 16;
data_cal[2] <= (data_cal[2] * {16'b0, gain_blue}) >> 16; data_cal[2] <= (data_cal[2] * {16'b0, gain_red}) >> 16;
end else begin end else begin
data_cal[0] <= data_cal[0] >> 8; data_cal[0] <= data_cal[0] >> 8;
data_cal[1] <= data_cal[1] >> 8; data_cal[1] <= data_cal[1] >> 8;

32
rtl/Color/ColorBlender_Pipeline.sv
View File

@ -1,5 +1,3 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像 // 三通道图像合成一个RGB图像
module ColorBlender_Pipeline #( module ColorBlender_Pipeline #(
parameter reg [4:0] DATA_WIDTH = 12, // 输入图像的色深 parameter reg [4:0] DATA_WIDTH = 12, // 输入图像的色深
@ -9,7 +7,9 @@ module ColorBlender_Pipeline #(
input wire reset, input wire reset,
input wire [DATA_WIDTH - 1:0] in_data[3], input wire [DATA_WIDTH - 1:0] in_data[3],
input wire [7:0] in_user,
output reg [OUT_DEPTH - 1:0] out_data[3], output reg [OUT_DEPTH - 1:0] out_data[3],
output wire [7:0] out_user,
input wire in_valid, input wire in_valid,
output wire out_valid, output wire out_valid,
@ -17,21 +17,18 @@ module ColorBlender_Pipeline #(
input wire in_ready, input wire in_ready,
output wire out_ready, output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output wire out_hsync,
output wire out_fsync,
// 颜色校正 // 颜色校正
input wire [15:0] gain_red, input wire [15:0] gain_red,
input wire [15:0] gain_green, input wire [15:0] gain_green,
input wire [15:0] gain_blue, input wire [15:0] gain_blue,
input wire enable input wire enable
); );
localparam PIPELINE = 4; localparam PIPELINE = 4;
reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid; reg [7:0] pipeline_user[PIPELINE];
reg [PIPELINE-1:0] pipeline_valid;
wire pipeline_flag; wire pipeline_flag;
assign pipeline_flag = (pipeline_valid[PIPELINE-1] == 0) | (in_ready); assign pipeline_flag = (pipeline_valid[PIPELINE-1] == 0) | (in_ready);
@ -39,9 +36,7 @@ module ColorBlender_Pipeline #(
assign out_ready = pipeline_flag; assign out_ready = pipeline_flag;
//out_valid ：只要本模块有数据要发送就一直拉高 //out_valid ：只要本模块有数据要发送就一直拉高
assign out_valid = pipeline_valid[PIPELINE-1]; assign out_valid = pipeline_valid[PIPELINE-1];
assign out_user = pipeline_user[PIPELINE-1];
assign out_hsync = pipeline_hsync[PIPELINE-1];
assign out_fsync = pipeline_fsync[PIPELINE-1];
reg [32 - 1:0] data_cal0[3]; reg [32 - 1:0] data_cal0[3];
reg [32 - 1:0] data_cal1[3]; reg [32 - 1:0] data_cal1[3];
@ -51,29 +46,28 @@ module ColorBlender_Pipeline #(
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
pipeline_valid <= 0; pipeline_valid <= 0;
pipeline_hsync <= 0;
pipeline_fsync <= 0;
for (i = 0; i < 3; i = i + 1) data_cal0[i] <= 0; for (i = 0; i < 3; i = i + 1) data_cal0[i] <= 0;
for (i = 0; i < 3; i = i + 1) data_cal1[i] <= 0; for (i = 0; i < 3; i = i + 1) data_cal1[i] <= 0;
for (i = 0; i < 3; i = i + 1) data_cal2[i] <= 0; for (i = 0; i < 3; i = i + 1) data_cal2[i] <= 0;
for (i = 0; i < 3; i = i + 1) out_data[i] <= 0; for (i = 0; i < 3; i = i + 1) out_data[i] <= 0;
for (i = 0; i < PIPELINE; i = i + 1) pipeline_user[i] <= 0;
end else if (pipeline_flag) begin end else if (pipeline_flag) begin
/************* 流水 ************/ /************* 流水 ************/
pipeline_valid <= {pipeline_valid[PIPELINE-2:0], in_valid}; pipeline_valid <= {pipeline_valid[PIPELINE-2:0], in_valid};
pipeline_hsync <= {pipeline_hsync[PIPELINE-2:0], in_hsync};
pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
/************* 1:计算1 ************/ /************* 1:计算1 ************/
if (in_valid) begin if (in_valid) begin
pipeline_user[0] <= in_user;
data_cal0[0] <= (in_data[0]) << (8 - (DATA_WIDTH - OUT_DEPTH)); data_cal0[0] <= (in_data[0]) << (8 - (DATA_WIDTH - OUT_DEPTH));
data_cal0[1] <= (in_data[1]) << (8 - (DATA_WIDTH - OUT_DEPTH)); data_cal0[1] <= (in_data[1]) << (8 - (DATA_WIDTH - OUT_DEPTH));
data_cal0[2] <= (in_data[2]) << (8 - (DATA_WIDTH - OUT_DEPTH)); data_cal0[2] <= (in_data[2]) << (8 - (DATA_WIDTH - OUT_DEPTH));
end end
/************* 2:计算2 ************/ /************* 2:计算2 ************/
if (pipeline_valid[0]) begin if (pipeline_valid[0]) begin
pipeline_user[1] <= pipeline_user[0];
if (enable) begin if (enable) begin
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_blue}) >> 16; data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16; data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_red}) >> 16; data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
end else begin end else begin
data_cal1[0] <= data_cal0[0] >> 8; data_cal1[0] <= data_cal0[0] >> 8;
data_cal1[1] <= data_cal0[1] >> 8; data_cal1[1] <= data_cal0[1] >> 8;
@ -82,12 +76,14 @@ module ColorBlender_Pipeline #(
end end
/************* 3:计算3 ************/ /************* 3:计算3 ************/
if (pipeline_valid[1]) begin if (pipeline_valid[1]) begin
pipeline_user[2] <= pipeline_user[1];
data_cal2[0] <= (|data_cal1[0][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[0]; data_cal2[0] <= (|data_cal1[0][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (|data_cal1[1][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[1]; data_cal2[1] <= (|data_cal1[1][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (|data_cal1[2][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[2]; data_cal2[2] <= (|data_cal1[2][31 : OUT_DEPTH]) ? {32{1'b1}} : data_cal1[2];
end end
/************* 4:发送结果 ************/ /************* 4:发送结果 ************/
if (pipeline_valid[2]) begin if (pipeline_valid[2]) begin
pipeline_user[3] <= pipeline_user[2];
out_data[0] <= data_cal2[0][OUT_DEPTH-1:0]; out_data[0] <= data_cal2[0][OUT_DEPTH-1:0];
out_data[1] <= data_cal2[1][OUT_DEPTH-1:0]; out_data[1] <= data_cal2[1][OUT_DEPTH-1:0];
out_data[2] <= data_cal2[2][OUT_DEPTH-1:0]; out_data[2] <= data_cal2[2][OUT_DEPTH-1:0];

2
rtl/Color/GammaCorrection.sv
View File

@ -1,5 +1,3 @@
`timescale 1ns / 1ps
module GammaCorrection #( module GammaCorrection #(
parameter reg [4:0] COLOR_DEPTH = 8 parameter reg [4:0] COLOR_DEPTH = 8
) ( ) (

91
rtl/Color/GammaCorrection_Pipeline.sv
View File

@ -1,42 +1,91 @@
`timescale 1ns / 1ps `include "common"
`include "vector"
`include "color"
module GammaCorrection_Pipeline module GammaCorrection_Pipeline
import common::*; import common::*;
#( #(
parameter bit [4:0] COLOR_DEPTH = 8 parameter uint COLOR_DEPTH = 8
) ( ) (
input var clk, input var clk,
input var reset, input var rst,
input var in_ready, input var i_ready,
input var in_valid, input var i_valid,
input var [COLOR_DEPTH - 1 : 0] in_data[3], input var [COLOR_DEPTH - 1 : 0] i_data[3],
output var out_ready, output var o_ready,
output var out_valid, output var o_valid,
output var [COLOR_DEPTH - 1 : 0] out_data[3], output var [COLOR_DEPTH - 1 : 0] o_data[3],
output var out_hsync, input var i_hsync,
output var out_fsync, input var i_fsync,
output var o_hsync,
output var o_fsync,
input var [7:0] in_Gtable[256], input var [COLOR_DEPTH - 1:0] i_Gtable[2 ** COLOR_DEPTH],
input var in_enable input var i_enable
); );
Color color; // pipeline level
localparam uint PIPELINELEVEL = 2;
assign out_ready = in_ready; // Define Color
`Typedef_Color(color_t, 8) color_t;
`Typedef_Vector(Vector_Color, color_t, PIPELINELEVEL - 1, PIPELINELEVEL - 1) Vector_Color;
Vector_Color color;
// shift queue: horizon sync and flame sync
`Typedef_Vector(Vector_Sync, bit, PIPELINELEVEL - 1, PIPELINELEVEL - 1) Vector_Sync;
Vector_Sync hsync, fsync;
always_ff @(posedge clock) begin : blockName // Pipeline status
if (reset) begin `Typedef_Vector(Vector_Pipe, bit, PIPELINELEVEL, PIPELINELEVEL) Vector_Pipe;
out_valid <= 0; Vector_Pipe pipeline_status;
out_data[0] <= 0;
out_data[1] <= 0; assign o_ready = i_ready;
out_data[2] <= 0;
// Pipeline in: Read data
always_ff @(posedge clk) begin : Pipeline_in
if (rst) begin
pipeline_status <= `Vector_Pipe::f_clearWith(0);
hsync <= `Vector_Sync::f_clearWith(0);
fsync <= `Vector_Sync::f_clearWith(0);
end else begin end else begin
// read sync edge signal and push front
hsync <= `Vector_Sync::f_pushFront(i_hsync, hsync);
fsync <= `Vector_Sync::f_pushFront(i_fsync, fsync);
// push front i_valid signal
pipeline_status <= `Vector_Pipe::f_pushFront(i_valid, pipeline_status);
// read color data
if (i_valid) begin
color <= `Vector_Color::f_pushFront(`color_t::f_fromRGB(i_data[2], i_data[1], i_data[0]), color);
end else begin
end
end
end end
// Pipeline 2: Send data
always_ff @(posedge clk) begin : Pipeline_1
if (rst) begin
o_data <= {0, 0, 0};
o_hsync <= 0;
o_fsync <= 0;
end else begin
// send the last sync signal from queue
o_hsync <= `Vector_Sync::f_getBack(hsync);
o_fsync <= `Vector_Sync::f_getBack(fsync);
// read adjust data from gamma table
// {o_data[2], o_data[1], o_data[0]} <= {
// i_Gtable[color.red], i_Gtable[color.green], i_Gtable[color.blue]
// };
o_valid <= 1;
end
end end

3
rtl/Color/GreyWorld.sv
View File

@ -1,6 +1,3 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像 // 三通道图像合成一个RGB图像
module GreyWorld #( module GreyWorld #(
parameter reg [4:0] COLOR_DEPTH = 8, parameter reg [4:0] COLOR_DEPTH = 8,

2
rtl/Color/SaturationCorrection.sv
View File

@ -1,5 +1,3 @@
`timescale 1ns / 1ps
module SaturationCorrection #( module SaturationCorrection #(
parameter reg [4:0] COLOR_DEPTH = 8 parameter reg [4:0] COLOR_DEPTH = 8
) ( ) (

2
rtl/Color/WhiteBalance.sv
View File

@ -1,5 +1,3 @@
`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像 // 三通道图像合成一个RGB图像
module WhiteBalance #( module WhiteBalance #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深 parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深

56
rtl/Common/color.svh Normal file
View File

@ -0,0 +1,56 @@
`ifndef __COLOR_SVH__
`define __COLOR_SVH__
`define Typedef_Color(Name, DataDeepth) \
`define Name Color#(Name, DataDeepth) \
`ifdef DEBUG \
typedef struct { \
bit [DataDeepth - 1:0] red; \
bit [DataDeepth - 1:0] green; \
bit [DataDeepth - 1:0] blue; \
} \
`else \
typedef struct packed { \
bit [DataDeepth - 1:0] red; \
bit [DataDeepth - 1:0] green; \
bit [DataDeepth - 1:0] blue; \
} \
`endif
class Color #(
type T,
int DEEPTH = 8
);
static function automatic T f_fromRGB(bit [DEEPTH - 1 : 0] red, bit [DEEPTH - 1 : 0] green,
bit [DEEPTH - 1 : 0] blue);
`ifdef DEBUG
T _color;
_color.red = red;
_color.green = green;
_color.blue = blue;
return _color;
`else
return {red, green, blue};
`endif
endfunction
static function automatic T f_fromBits(bit [DEEPTH * 3 - 1 : 0] data);
`ifdef DEBUG
T _color;
_color.red = data[DEEPTH*3-1-:DEEPTH];
_color.green = data[DEEPTH*2-1-:DEEPTH];
_color.blue = data[DEEPTH*1-1-:DEEPTH];
return _color;
`else
return {data};
`endif
endfunction
static function automatic bit [DEEPTH * 3 - 1 : 0] f_toBits(T color);
return {color.red, color.green, color.blue};
endfunction
endclass
`endif

24
rtl/Common/common.svh Normal file
View File

@ -0,0 +1,24 @@
`ifndef __COMMON_SVH__
`define __COMMON_SVH__
`default_nettype none
`define STRING(String) String
package common;
typedef bit [31:0] uint32_t;
typedef bit [15:0] uint16_t;
typedef bit [7:0] uint8_t;
typedef uint32_t uint;
// typedef struct {
// bit [DEEPTH - 1:0] red;
// bit [DEEPTH - 1:0] green;
// bit [DEEPTH - 1:0] blue;
// } color_t;
endpackage
`endif

87
rtl/Common/vector.svh Normal file
View File

@ -0,0 +1,87 @@
`ifndef __VECTOR_SVH__
`define __VECTOR_SVH__
`include "common"
`define Typedef_Vector(Name, DataType, DataDeepth, SizeDeepth) \
`define `STRING(Name) Vector#(Name, DataType, DataDeepth, SizeDeepth) \
`ifdef DEBUG \
typedef struct { \
`STRING(DataType) data[DataDeepth]; \
bit [SizeDeepth - 1 : 0] size; \
} \
`else \
typedef struct packed { \
`STRING(DataType) [DataDeepth:0] data; \
bit [SizeDeepth - 1 : 0] size; \
} \
`endif
class Vector #(
type ARRAY_TYPE,
type BASIC_TYPE,
int DATA_DEEPTH = 8,
int SIZE_DEEPTH = 8
);
// `ifdef DEBUG
// typedef struct {
// T data[DATA_DEEPTH];
// bit [SIZE_DEEPTH - 1 : 0] size;
// } ARRAY_TYPE;
// `else
// typedef struct packed {
// T [DATA_DEEPTH:0] data;
// bit [SIZE_DEEPTH - 1 : 0] size;
// } ARRAY_TYPE;
// `endif
// Get the size of Vector
static function automatic bit [SIZE_DEEPTH - 1 : 0] f_getSize(ARRAY_TYPE _vector);
return _vector.size;
endfunction //automatic
static function automatic ARRAY_TYPE f_fill(BASIC_TYPE data);
`ifdef DEBUG
ARRAY_TYPE _vector;
for (int i = 0; i < DATA_DEEPTH; ++i) _vector.data[i] = data;
_vector.size = DATA_DEEPTH;
return _vector;
`else
return {{DATA_DEEPTH{data}}, DATA_DEEPTH};
`endif
endfunction //automatic
static function automatic ARRAY_TYPE f_clearWith(BASIC_TYPE data);
`ifdef DEBUG
ARRAY_TYPE _vector;
for (int i = 0; i < DATA_DEEPTH; ++i) _vector.data[i] = data;
_vector.size = 0;
return _vector;
`else
return {{DATA_DEEPTH{data}}, {SIZE_DEEPTH{1'b0}}};
`endif
endfunction
// Push data into front Vector
static function automatic ARRAY_TYPE f_pushFront(BASIC_TYPE data, ARRAY_TYPE _vector);
`ifdef DEBUG
for (int i = 1; i < DATA_DEEPTH; ++i) _vector.data[i] = _vector.data[i-1];
`else
_vector.data = _vector.data >> DATA_DEEPTH;
`endif
_vector.data[0] = data;
_vector.size = _vector.size + 1;
return _vector;
endfunction //automatic
// Get the last data of the Vector
static function automatic BASIC_TYPE f_getBack(ARRAY_TYPE _vector);
return _vector.data[DATA_DEEPTH-1];
endfunction //automatic
endclass
`endif

1
rtl/Crop/Crop.sv
View File

@ -1,4 +1,3 @@
`timescale 1ns/1ps
module Crop #( module Crop #(
parameter reg [15:0] IN_WIDTH = 1934, parameter reg [15:0] IN_WIDTH = 1934,
parameter reg [15:0] IN_HEIGHT = 1086, parameter reg [15:0] IN_HEIGHT = 1086,

85
rtl/Crop/Crop_Pipeline.sv
View File

@ -1,4 +1,3 @@
`timescale 1ns / 1ps
module Crop_Pipeline #( module Crop_Pipeline #(
parameter IN_WIDTH = 512, parameter IN_WIDTH = 512,
parameter IN_HEIGHT = 512, parameter IN_HEIGHT = 512,
@ -15,88 +14,100 @@ module Crop_Pipeline #(
input wire reset, input wire reset,
input wire [COLOR_DEPTH - 1:0] in_data [3], input wire [COLOR_DEPTH - 1:0] in_data [3],
input wire [7:0] in_user,
output reg [COLOR_DEPTH - 1:0] out_data [3], output reg [COLOR_DEPTH - 1:0] out_data [3],
output wire [7:0] out_user,
input wire in_valid, input wire in_valid,
output reg out_valid, output reg out_valid,
input wire in_ready, input wire in_ready,
output wire out_ready, output wire out_ready
input wire in_hsync,
input wire in_fsync,
output reg out_hsync,
output reg out_fsync
); );
localparam PIPILINE = 3; wire in_fstart, in_hstart;
reg out_fstart, out_hstart;
assign in_fstart = in_user[1];
assign in_hstart = in_user[0];
reg [PIPILINE-1:0] pipeline_valid; localparam PIPELINE = 3;
reg [5:0] pipeline_user[PIPELINE];
reg [PIPELINE-1:0] pipeline_valid;
wire pipeline_running; wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1]; assign pipeline_running = in_ready | ~pipeline_valid[PIPELINE-1];
reg [31:0] cnt_x, cnt_y, temp_x, temp_y; reg [31:0] cnt_x, cnt_y, temp_x, temp_y;
reg force_dis, force_en; reg force_dis;
reg [COLOR_DEPTH-1:0] data_cache0[3]; reg [COLOR_DEPTH-1:0] data_cache0[3];
reg [COLOR_DEPTH-1:0] data_cache1[3]; reg [COLOR_DEPTH-1:0] data_cache1[3];
//out_ready ：只要本模块可以接收数据就一直拉高 //out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_running; assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高 //out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = (pipeline_valid[PIPILINE-1] & ~force_dis) | force_en; assign out_valid = (pipeline_valid[PIPELINE-1] & ~force_dis);
assign out_user = {pipeline_user[PIPELINE-1],out_fstart,out_hstart};
//分别表示当前像素: 显示；被裁掉；空。 //分别表示当前像素: 显示；被裁掉；空。
reg [1:0] flag_crop; reg flag_crop;
localparam CROP_ERROR = 2'b00, CROP_KEEP = 2'b01, CROP_GIVE_UP = 2'b10, CROP_BLANK = 2'b11; localparam CROP_KEEP = 1'b0,
CROP_GIVE_UP = 1'b1;
integer i; integer i;
always @(posedge clk) begin
if(reset) for(i=0;i<3;i=i+1) data_cache0[i] <= 0;
else if(pipeline_running & in_valid) for(i=0;i<3;i++) data_cache0[i] <= in_data[i];
else for(i=0;i<3;i=i+1) data_cache0[i] <= data_cache0[i];
end
always @(posedge clk) begin
if(reset) for(i=0;i<3;i=i+1) data_cache1[i] <= 0;
else if(pipeline_running & pipeline_valid[0]) for(i=0;i<3;i++) data_cache1[i] <= data_cache0[i];
else for(i=0;i<3;i=i+1) data_cache1[i] <= data_cache1[i];
end
always @(posedge clk) begin always @(posedge clk) begin
if(reset) begin if(reset) begin
pipeline_valid <= 0; pipeline_valid <= 0;
cnt_x <= 0; cnt_x <= 0;
cnt_y <= 0; cnt_y <= 0;
for (i = 0; i < 3; i++) data_cache0[i] <= 0;
for (i = 0; i < 3; i++) data_cache1[i] <= 0; for(i=0;i<3;i=i+1) out_data[i] <= 0;
for (i = 0; i < 3; i++) out_data[i] <= 0;
flag_crop <= 0; flag_crop <= 0;
force_dis <= 0; force_dis <= 0;
force_en <= 0; out_hstart <= 0;
out_hsync <= 0; out_fstart <= 0;
out_fsync <= 0;
temp_x <= 0; temp_x <= 0;
temp_y <= 0; temp_y <= 0;
for(i=0;i<PIPELINE;i=i+1) pipeline_user[i] <= 0;
end else if(pipeline_running) begin end else if(pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid}; pipeline_valid <= {pipeline_valid[PIPELINE-2:0],in_valid};
if(in_valid) begin //when 00 if(in_valid) begin //when 00
for (i = 0; i < 3; i++) data_cache0[i] <= in_data[i]; pipeline_user[0] <= in_user[7:2];
cnt_x <= (in_hsync) ? (0) : (cnt_x + 1); cnt_x <= (in_hstart)?(0):(cnt_x+1);
cnt_y <= (in_hsync) ? ((in_fsync) ? (0) : (cnt_y + 1)) : (cnt_y); cnt_y <= (in_hstart)?((in_fstart)?(0):(cnt_y+1)):(cnt_y);
end end
if(pipeline_valid[0]) begin //when 00 if(pipeline_valid[0]) begin //when 00
for (i = 0; i < 3; i++) data_cache1[i] <= data_cache0[i]; pipeline_user[1] <= pipeline_user[0];
temp_x <= cnt_x; temp_x <= cnt_x;
temp_y <= cnt_y; temp_y <= cnt_y;
if(cnt_x < OFFSET_X || cnt_y < OFFSET_Y) flag_crop <= CROP_GIVE_UP; if(cnt_x < OFFSET_X || cnt_y < OFFSET_Y) flag_crop <= CROP_GIVE_UP;
else if (cnt_x < OFFSET_X + OUT_WIDTH && cnt_y < OFFSET_Y + OUT_HEIGHT) begin else if(cnt_x < OFFSET_X + OUT_WIDTH && cnt_y < OFFSET_Y + OUT_HEIGHT) flag_crop <= CROP_KEEP;
if (cnt_x < IN_WIDTH && cnt_y < IN_HEIGHT) flag_crop <= CROP_KEEP; else flag_crop <= CROP_GIVE_UP;
else flag_crop <= CROP_BLANK;
end else flag_crop <= CROP_ERROR;
end end
if(pipeline_valid[1]) begin if(pipeline_valid[1]) begin
pipeline_user[2] <= pipeline_user[1];
for(i=0;i<3;i++) out_data[i] <= data_cache1[i]; for(i=0;i<3;i++) out_data[i] <= data_cache1[i];
out_hsync <= (temp_x == OFFSET_X) && (temp_y >= OFFSET_Y); out_hstart <= (temp_x == OFFSET_X) && (temp_y >= OFFSET_Y);
out_fsync <= (temp_x == OFFSET_X) && (temp_y == OFFSET_Y); out_fstart <= (temp_x == OFFSET_X) && (temp_y == OFFSET_Y);
case (flag_crop) case (flag_crop)
CROP_ERROR: {force_dis, force_en} <= {1'b1, 1'b0}; CROP_KEEP : force_dis <= 1'b0;
CROP_KEEP: {force_dis, force_en} <= {1'b0, 1'b0}; CROP_GIVE_UP : force_dis <= 1'b1;
CROP_GIVE_UP: {force_dis, force_en} <= {1'b1, 1'b0};
CROP_BLANK:
{force_dis, force_en} <= {1'b0, 1'b0}; //应该是01, 但我还没写BLANK逻辑
endcase endcase
end end
end end

2
rtl/RAM/DiffWidthSyncFIFO.sv
View File

@ -1,5 +1,3 @@
`timescale 1ns / 1ps
module DiffWidthSyncFIFO #( module DiffWidthSyncFIFO #(
parameter reg [7:0] DATA_WIDTH = 8, parameter reg [7:0] DATA_WIDTH = 8,
parameter reg [7:0] DATA_DEPTH = 12, parameter reg [7:0] DATA_DEPTH = 12,

2
rtl/RAM/RGB_to_RAM.v
View File

@ -1,5 +1,3 @@
`timescale 1ns/1ps
module RGB_to_RAM #( module RGB_to_RAM #(
parameter COLOR_DEPTH = 8, parameter COLOR_DEPTH = 8,
parameter FIFO_SIZE = 128 parameter FIFO_SIZE = 128

2
rtl/RAM/tb_DiffWidthSyncFIFO.sv
View File

@ -1,5 +1,3 @@
`timescale 1ns / 1ps
`include "DiffWidthSyncFIFO.v"
`default_nettype none `default_nettype none
module tb_DiffWidthSyncFIFO; module tb_DiffWidthSyncFIFO;

1726
rtl/SimLib/Camera2ISP_fifo.v Normal file
View File

File diff suppressed because it is too large Load Diff

73
rtl/SimLib/Gowin_SDPB.v Normal file
View File

@ -0,0 +1,73 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//Tool Version: V1.9.10.02
//Part Number: GW5AST-LV138FPG676AES
//Device: GW5AST-138
//Device Version: B
//Created Time: Fri Oct 18 16:47:41 2024
module Gowin_SDPB (dout, clka, cea, clkb, ceb, oce, reset, ada, din, adb);
output [15:0] dout;
input clka;
input cea;
input clkb;
input ceb;
input oce;
input reset;
input [10:0] ada;
input [15:0] din;
input [10:0] adb;
wire [23:0] sdpb_inst_0_dout_w;
wire [23:0] sdpb_inst_1_dout_w;
wire gw_gnd;
assign gw_gnd = 1'b0;
SDPB sdpb_inst_0 (
.DO({sdpb_inst_0_dout_w[23:0],dout[7:0]}),
.CLKA(clka),
.CEA(cea),
.CLKB(clkb),
.CEB(ceb),
.OCE(oce),
.RESET(reset),
.BLKSELA({gw_gnd,gw_gnd,gw_gnd}),
.BLKSELB({gw_gnd,gw_gnd,gw_gnd}),
.ADA({ada[10:0],gw_gnd,gw_gnd,gw_gnd}),
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7:0]}),
.ADB({adb[10:0],gw_gnd,gw_gnd,gw_gnd})
);
defparam sdpb_inst_0.READ_MODE = 1'b0;
defparam sdpb_inst_0.BIT_WIDTH_0 = 8;
defparam sdpb_inst_0.BIT_WIDTH_1 = 8;
defparam sdpb_inst_0.BLK_SEL_0 = 3'b000;
defparam sdpb_inst_0.BLK_SEL_1 = 3'b000;
defparam sdpb_inst_0.RESET_MODE = "SYNC";
SDPB sdpb_inst_1 (
.DO({sdpb_inst_1_dout_w[23:0],dout[15:8]}),
.CLKA(clka),
.CEA(cea),
.CLKB(clkb),
.CEB(ceb),
.OCE(oce),
.RESET(reset),
.BLKSELA({gw_gnd,gw_gnd,gw_gnd}),
.BLKSELB({gw_gnd,gw_gnd,gw_gnd}),
.ADA({ada[10:0],gw_gnd,gw_gnd,gw_gnd}),
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[15:8]}),
.ADB({adb[10:0],gw_gnd,gw_gnd,gw_gnd})
);
defparam sdpb_inst_1.READ_MODE = 1'b0;
defparam sdpb_inst_1.BIT_WIDTH_0 = 8;
defparam sdpb_inst_1.BIT_WIDTH_1 = 8;
defparam sdpb_inst_1.BLK_SEL_0 = 3'b000;
defparam sdpb_inst_1.BLK_SEL_1 = 3'b000;
defparam sdpb_inst_1.RESET_MODE = "SYNC";
endmodule //Gowin_SDPB

50
rtl/SimLib/Gowin_SDPB_USER.v Normal file
View File

@ -0,0 +1,50 @@
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
//All rights reserved.
//File Title: IP file
//Tool Version: V1.9.10.02
//Part Number: GW5AST-LV138FPG676AES
//Device: GW5AST-138
//Device Version: B
//Created Time: Fri Nov 1 11:18:28 2024
module Gowin_SDPB_USER (dout, clka, cea, clkb, ceb, oce, reset, ada, din, adb);
output [7:0] dout;
input clka;
input cea;
input clkb;
input ceb;
input oce;
input reset;
input [10:0] ada;
input [7:0] din;
input [10:0] adb;
wire [23:0] sdpb_inst_0_dout_w;
wire gw_gnd;
assign gw_gnd = 1'b0;
SDPB sdpb_inst_0 (
.DO({sdpb_inst_0_dout_w[23:0],dout[7:0]}),
.CLKA(clka),
.CEA(cea),
.CLKB(clkb),
.CEB(ceb),
.OCE(oce),
.RESET(reset),
.BLKSELA({gw_gnd,gw_gnd,gw_gnd}),
.BLKSELB({gw_gnd,gw_gnd,gw_gnd}),
.ADA({ada[10:0],gw_gnd,gw_gnd,gw_gnd}),
.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7:0]}),
.ADB({adb[10:0],gw_gnd,gw_gnd,gw_gnd})
);
defparam sdpb_inst_0.READ_MODE = 1'b0;
defparam sdpb_inst_0.BIT_WIDTH_0 = 8;
defparam sdpb_inst_0.BIT_WIDTH_1 = 8;
defparam sdpb_inst_0.BLK_SEL_0 = 3'b000;
defparam sdpb_inst_0.BLK_SEL_1 = 3'b000;
defparam sdpb_inst_0.RESET_MODE = "SYNC";
endmodule //Gowin_SDPB_USER

22316
rtl/SimLib/prim_sim.v Normal file
View File

File diff suppressed because it is too large Load Diff

16
rtl/common.sv
View File

@ -1,16 +0,0 @@
`default_nettype none
package common;
class Color;
bit [7:0] red;
bit [7:0] green;
bit [7:0] blue;
function new(bit [7:0] red, bit [7:0] green, bit [7:0] blue);
this.red = red;
this.green = green;
this.blue = blue;
endfunction //new()
endclass //Color
endpackage

1
rtl/isp.sv
View File

@ -1,4 +1,3 @@
`timescale 1ns/1ps
module isp #( module isp #(
parameter reg [15:0] IN_WIDTH = 1936, parameter reg [15:0] IN_WIDTH = 1936,
parameter reg [15:0] IN_HEIGHT = 1088, parameter reg [15:0] IN_HEIGHT = 1088,

239
rtl/isp_Pipeline.sv
View File

@ -1,4 +1,3 @@
`timescale 1ns / 1ps
/* TODO 1. ISP寄存器配置模式，如配置是否启用什么什么矫正，矫正系数多少。能读能写。选好通信协议，要不要用AXI？ /* TODO 1. ISP寄存器配置模式，如配置是否启用什么什么矫正，矫正系数多少。能读能写。选好通信协议，要不要用AXI？
2. 白平衡，GAMMA矫正。白平衡做RAW白平衡吗？ 2. 白平衡，GAMMA矫正。白平衡做RAW白平衡吗？
3. 寄存器中应该有一个寄存器标识ISP运行状态。比如裁切模块，直接修改寄存器值数据就乱了。 3. 寄存器中应该有一个寄存器标识ISP运行状态。比如裁切模块，直接修改寄存器值数据就乱了。
@ -7,31 +6,39 @@
6. ISP不应该只有一条线，比如存进SDRAM后，读出来时也可以做处理。 6. ISP不应该只有一条线，比如存进SDRAM后，读出来时也可以做处理。
*/ */
module isp_Pipeline #( module isp_Pipeline #(
`ifdef DEBUG
parameter reg [15:0] DATA_WIDTH = 16,
parameter reg [15:0] IN_WIDTH = 120,
parameter reg [15:0] IN_HEIGHT = 120,
parameter reg [15:0] OUT_WIDTH = 100,
parameter reg [15:0] OUT_HEIGHT = 100,
`else
parameter reg [15:0] DATA_WIDTH = 12, parameter reg [15:0] DATA_WIDTH = 12,
parameter reg [15:0] IN_WIDTH = 1936, parameter reg [15:0] IN_WIDTH = 1936,
parameter reg [15:0] IN_HEIGHT = 1088, parameter reg [15:0] IN_HEIGHT = 1088,
parameter OFFSET_X = 7,
parameter OFFSET_Y = 3,
parameter reg [15:0] OUT_WIDTH = 1920, parameter reg [15:0] OUT_WIDTH = 1920,
parameter reg [15:0] OUT_HEIGHT = 1080, parameter reg [15:0] OUT_HEIGHT = 1080,
`endif
parameter OFFSET_X = 7,
parameter OFFSET_Y = 3,
parameter reg [ 4:0] COLOR_DEPTH = 8, // Can't Change!!! parameter reg [ 4:0] COLOR_DEPTH = 8, // Can't Change!!!
parameter reg [ 1:0] RAW_TYPE = 3 // 0:grbg 1:rggb 2:bggr 3:gbrg parameter reg [ 1:0] RAW_TYPE = 0 // 0:grbg 1:rggb 2:bggr 3:gbrg
) ( ) (
// 基本信号 // 基本信号
input wire clk, input wire camera_clk,
input wire isp_clk,
input wire reset, input wire reset,
// 数据线
input wire [DATA_WIDTH-1:0] in_data, // 数据输入线
output wire [3 * COLOR_DEPTH - 1:0] out_data,
output wire fsync,
output wire hsync,
// 数据有效信号
input wire in_valid, input wire in_valid,
output wire out_valid, input wire [DATA_WIDTH-1:0] in_data, // 数据输入线
input wire in_fsync, // 帧同步，在两帧间隔间拉高，标志着一帧的结束和新帧的开始
input wire in_hsync, // 行同步，在一行内持续拉高，一行结束后拉低。
// 准备信号 output wire out_valid,
output wire [3 * COLOR_DEPTH - 1:0] out_data, // 数据输出线
output wire [7:0] out_user, //自定义数据线. [0]是hstart标志位, [1]是fstart标志位
// 准备信号 暂时没用
input wire in_ready, input wire in_ready,
output wire out_ready, output wire out_ready,
@ -39,113 +46,193 @@ module isp_Pipeline #(
input wire [15:0] gain_red, input wire [15:0] gain_red,
input wire [15:0] gain_green, input wire [15:0] gain_green,
input wire [15:0] gain_blue, input wire [15:0] gain_blue,
input wire blender_enable // 是否启用颜色校正 input wire blender_enable, // 是否启用颜色校正
output wire fifo_isp_adapter_h_pixel_correct,
output wire fifo_isp_adapter_v_pixel_correct
); );
wire [DATA_WIDTH-1:0] DPC_data; wire [DATA_WIDTH-1:0] DPC_data;
wire [DATA_WIDTH-1:0] adapter_data;
wire [7:0] Windows_DPC_user, DPC_user, Windows_Demosaic_user, adapter_user, Demosaic_user, Blender_user, Crop_user;
wire [DATA_WIDTH-1:0] Demosaic_data[3]; wire [DATA_WIDTH-1:0] Demosaic_data[3];
wire [DATA_WIDTH-1:0] Windows_DPC_data[5*5]; wire [DATA_WIDTH-1:0] Windows_DPC_data[5*5];
wire [DATA_WIDTH-1:0] Windows_Demosaic_data[3*3]; wire [DATA_WIDTH-1:0] Windows_Demosaic_data[3*3];
wire [COLOR_DEPTH - 1 : 0] Blender_data[3]; wire [COLOR_DEPTH - 1 : 0] Blender_data[3];
wire [COLOR_DEPTH - 1 : 0] Crop_data[3]; wire [COLOR_DEPTH - 1 : 0] Crop_data[3];
wire Windows_DPC_valid, DPC_valid, Windows_Demosaic_valid, Demosaic_valid, Blender_valid, Crop_valid; wire adapter_valid, Windows_DPC_valid, DPC_valid, Windows_Demosaic_valid, Demosaic_valid, Blender_valid, Crop_valid;
wire Windows_DPC_ready, DPC_ready, Windows_Demosaic_ready, Demosaic_ready, Blender_ready, Crop_ready; wire Windows_DPC_ready, DPC_ready, Windows_Demosaic_ready, Demosaic_ready, Blender_ready, Crop_ready;
wire Demosaic_hsync, Blender_hsync, Crop_hsync;
wire Demosaic_fsync, Blender_fsync, Crop_fsync;
assign out_valid = Crop_valid; assign out_valid = Crop_valid;
assign out_ready = Windows_DPC_ready; assign out_ready = Windows_DPC_ready;
assign out_data = {Crop_data[2], Crop_data[1], Crop_data[0]}; assign out_data = {Crop_data[2], Crop_data[1], Crop_data[0]};
assign fsync = Crop_fsync; assign out_user = Crop_user;
assign hsync = Crop_hsync;
fifo_isp_adapter #(
.DATA_WIDTH(DATA_WIDTH)
) fifo_isp_adapter_u (
.reset(reset),
.camera_clk(camera_clk),
.in_valid(in_valid),
.in_data(in_data),
.in_fsync(in_fsync),
.in_hsync(in_hsync),
.isp_clk (isp_clk),
.out_valid(adapter_valid),
.out_data (adapter_data),
.out_user (adapter_user)
);
frame_size_detect u_frame_size_detect (
.clk (isp_clk),
.reset (reset),
.in_valid (adapter_valid),
.hstart (adapter_user[0]),
.fstart (adapter_user[1]),
.h_pixel (IN_WIDTH),
.v_pixel (IN_HEIGHT),
.h_pixel_correct(fifo_isp_adapter_h_pixel_correct),
.v_pixel_correct(fifo_isp_adapter_v_pixel_correct)
);
// wire [7:0] wr_data, wr_addr;
// wire wr_enable;
// wire [8*16-1:0] isp_vector;
// isp_register_ctrl isp_register_ctrl(
// .clk (isp_clk),
// .reset (reset),
// .wr_data (wr_data),
// .wr_enable(wr_enable),
// .wr_addr (wr_addr),
// .vector (isp_vector)
// )
Windows #( Windows #(
.DATA_WIDTH (DATA_WIDTH), .DATA_WIDTH (DATA_WIDTH),
.IMAGE_WIDTH (IN_WIDTH),
.WINDOWS_WIDTH (5), .WINDOWS_WIDTH (5),
.WINDOWS_ANCHOR_X(2), .WINDOWS_ANCHOR_X(2),
.WINDOWS_ANCHOR_Y(2) .WINDOWS_ANCHOR_Y(2)
) Windows_DPC_inst ( ) Windows_DPC_inst (
.clk (clk), .clk (isp_clk),
.reset(reset), .reset(reset),
.in_data (in_data),
.out_data (Windows_DPC_data), .in_valid(adapter_valid),
.in_valid (in_valid), .in_data (adapter_data),
.in_user (adapter_user),
.out_valid(Windows_DPC_valid), .out_valid(Windows_DPC_valid),
.out_data (Windows_DPC_data),
.out_user (Windows_DPC_user),
.in_ready (DPC_ready), .in_ready (DPC_ready),
.out_ready(Windows_DPC_ready) .out_ready(Windows_DPC_ready)
); );
DPC #( DPC #(
.TOTAL_WIDTH (IN_WIDTH),
.TOTAL_HEIGHT (IN_HEIGHT),
.RAW_TYPE (3), .RAW_TYPE (3),
.DATA_WIDTH (DATA_WIDTH), .DATA_WIDTH (DATA_WIDTH),
.THRESHOLD (50),
.MODULE_ENABLE(1), .MODULE_ENABLE(1),
.LABLE_ENABLE (1) .LABLE_ENABLE (0)
) DPC_inst ( ) DPC_inst (
.clk (clk), .clk (isp_clk),
.reset(reset), .reset(reset),
.in_data (Windows_DPC_data),
.out_data (DPC_data),
.in_valid(Windows_DPC_valid), .in_valid(Windows_DPC_valid),
.in_data (Windows_DPC_data),
.in_user (Windows_DPC_user),
.out_valid(DPC_valid), .out_valid(DPC_valid),
.out_data (DPC_data),
.out_user (DPC_user),
.in_ready (Windows_Demosaic_ready), .in_ready (Windows_Demosaic_ready),
.out_ready(DPC_ready) .out_ready(DPC_ready)
); );
Windows #( Windows #(
.DATA_WIDTH (DATA_WIDTH), .DATA_WIDTH (DATA_WIDTH),
.IMAGE_WIDTH (IN_WIDTH),
.WINDOWS_WIDTH (3), .WINDOWS_WIDTH (3),
.WINDOWS_ANCHOR_X(1), .WINDOWS_ANCHOR_X(1),
.WINDOWS_ANCHOR_Y(1) .WINDOWS_ANCHOR_Y(1)
) Windows_Demosaic_inst ( ) Windows_Demosaic_inst (
.clk (clk), .clk (isp_clk),
.reset(reset), .reset(reset),
.in_data (DPC_data),
.out_data (Windows_Demosaic_data),
.in_valid(DPC_valid), .in_valid(DPC_valid),
.in_data (DPC_data),
.in_user (DPC_user),
.out_valid(Windows_Demosaic_valid), .out_valid(Windows_Demosaic_valid),
.out_data (Windows_Demosaic_data),
.out_user (Windows_Demosaic_user),
.in_ready (Demosaic_ready), .in_ready (Demosaic_ready),
.out_ready(Windows_Demosaic_ready) .out_ready(Windows_Demosaic_ready)
); );
// Windows #(
// .DATA_WIDTH (DATA_WIDTH),
// .WINDOWS_WIDTH (3 ),
// .WINDOWS_ANCHOR_X(1 ),
// .WINDOWS_ANCHOR_Y(1 )
// )Windows_Demosaic_inst(
// .clk (isp_clk ),
// .reset (reset ),
// .in_valid (adapter_valid ),
// .in_data (adapter_data ),
// .in_user (adapter_user ),
// .out_valid (Windows_Demosaic_valid ),
// .out_data (Windows_Demosaic_data ),
// .out_user (Windows_Demosaic_user ),
// .in_ready (Demosaic_ready ),
// .out_ready (Windows_Demosaic_ready )
// );
Demosaic_Pipeline #( Demosaic_Pipeline #(
.DATA_WIDTH (DATA_WIDTH),
.WINDOW_LENGTH(3), .WINDOW_LENGTH(3),
.TOTAL_WIDTH (IN_WIDTH), .RAW_TYPE (0)
.TOTAL_HEIGHT (IN_HEIGHT),
.RAW_TYPE (0),
.DATA_WIDTH (DATA_WIDTH)
) Demosaic_inst ( ) Demosaic_inst (
.clk (clk), .clk (isp_clk),
.reset(reset), .reset(reset),
.in_data (Windows_Demosaic_data),
.out_data (Demosaic_data),
.in_valid(Windows_Demosaic_valid), .in_valid(Windows_Demosaic_valid),
.in_data (Windows_Demosaic_data),
.in_user (Windows_Demosaic_user),
.out_valid(Demosaic_valid), .out_valid(Demosaic_valid),
.out_data (Demosaic_data),
.out_user (Demosaic_user),
.in_ready (Blender_ready), .in_ready (Blender_ready),
.out_ready(Demosaic_ready), .out_ready(Demosaic_ready)
.out_hsync(Demosaic_hsync),
.out_fsync(Demosaic_fsync)
); );
ColorBlender_Pipeline #( ColorBlender_Pipeline #(
.DATA_WIDTH(DATA_WIDTH), // 输入图像的色深 .DATA_WIDTH(DATA_WIDTH), // 输入图像的色深
.OUT_DEPTH (COLOR_DEPTH) // 输出图像的色深 .OUT_DEPTH (COLOR_DEPTH) // 输出图像的色深
) ColorBlender_inst ( ) ColorBlender_inst (
.clk (clk), .clk (isp_clk),
.reset(reset), .reset(reset),
.in_data (Demosaic_data),
.out_data (Blender_data),
.in_valid(Demosaic_valid), .in_valid(Demosaic_valid),
.in_data (Demosaic_data),
.in_user (Demosaic_user),
.out_valid(Blender_valid), .out_valid(Blender_valid),
.out_data (Blender_data),
.out_user (Blender_user),
.in_ready (Crop_ready), .in_ready (Crop_ready),
.out_ready(Blender_ready), .out_ready(Blender_ready),
.in_hsync (Demosaic_hsync),
.in_fsync (Demosaic_fsync),
.out_hsync(Blender_hsync),
.out_fsync(Blender_fsync),
.gain_red (gain_red), .gain_red (gain_red),
.gain_green(gain_green), .gain_green(gain_green),
@ -153,6 +240,35 @@ module isp_Pipeline #(
.enable (blender_enable) .enable (blender_enable)
); );
// wire [COLOR_DEPTH-1:0] adapter_data3[3];
// assign adapter_data3[0] = {adapter_data};
// assign adapter_data3[1] = {adapter_data};
// assign adapter_data3[2] = {adapter_data};
// Crop #(
// .IN_WIDTH (IN_WIDTH ),
// .IN_HEIGHT (IN_HEIGHT ),
// .OFFSET_X (OFFSET_X ),
// .OFFSET_Y (OFFSET_Y ),
// .OUT_WIDTH (OUT_WIDTH ),
// .OUT_HEIGHT (OUT_HEIGHT ),
// .COLOR_DEPTH(COLOR_DEPTH)
// ) Crop_inst(
// .clk (isp_clk ),
// .reset (reset ),
// .in_valid (adapter_valid ),
// .in_data (adapter_data3 ),
// .in_user (adapter_user ),
// .out_valid (Crop_valid ),
// .out_data (Crop_data ),
// .out_user (Crop_user ),
// .in_ready (in_ready ),
// .out_ready (Crop_ready )
// );
Crop_Pipeline #( Crop_Pipeline #(
.IN_WIDTH (IN_WIDTH ), .IN_WIDTH (IN_WIDTH ),
.IN_HEIGHT (IN_HEIGHT ), .IN_HEIGHT (IN_HEIGHT ),
@ -162,18 +278,19 @@ module isp_Pipeline #(
.OUT_HEIGHT (OUT_HEIGHT ), .OUT_HEIGHT (OUT_HEIGHT ),
.COLOR_DEPTH(COLOR_DEPTH) .COLOR_DEPTH(COLOR_DEPTH)
) Crop_inst ( ) Crop_inst (
.clk (clk), .clk (isp_clk),
.reset(reset), .reset(reset),
.in_data (Blender_data),
.out_data (Crop_data),
.in_valid(Blender_valid), .in_valid(Blender_valid),
.in_data (Blender_data),
.in_user (Blender_user),
.out_valid(Crop_valid), .out_valid(Crop_valid),
.out_data (Crop_data),
.out_user (Crop_user),
.in_ready (in_ready), .in_ready (in_ready),
.out_ready(Crop_ready), .out_ready(Crop_ready)
.in_hsync (Blender_hsync),
.in_fsync (Blender_fsync),
.out_hsync(Crop_hsync),
.out_fsync(Crop_fsync)
); );
// reg [15:0] data_out_temp[8192]; // reg [15:0] data_out_temp[8192];
@ -202,4 +319,6 @@ module isp_Pipeline #(
// end // end
// end // end
GSR GSR (.GSRI(1'b1));
endmodule endmodule

1
rtl/isp_Pipeline_tb.sv
View File

@ -1,4 +1,3 @@
`timescale 1ns / 1ps
module isp_tb(); module isp_tb();
parameter IN_WIDTH = 50; parameter IN_WIDTH = 50;

98
src/modules_tb/example_tb.cpp Normal file
View File

@ -0,0 +1,98 @@
// For read and write
#include <array>
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#include <fstream>
#include <ios>
#include <iostream>
#include <vector>
// SystemC global header
#include "sysc/communication/sc_clock.h"
#include "sysc/communication/sc_signal.h"
#include "sysc/communication/sc_signal_ifs.h"
#include "sysc/kernel/sc_module.h"
#include <memory>
#include <systemc>
// Include common routines
#include "sysc/kernel/sc_time.h"
#include "verilated_fst_sc.h"
#include <sys/stat.h> // mkdir
#include <utility>
#include <verilated.h>
// Include model
#include "Vtb.h"
using namespace sc_core;
using namespace sc_dt;
int sc_main(int argc, char *argv[]) {
std::cout << "Enter into sc_main\n";
// Create logs/ directory in case we have traces to put under it
Verilated::mkdir("logs");
// Set debug level, 0 is off, 9 is highest presently used
// May be overridden by commandArgs argument parsing
Verilated::debug(0);
// Randomization reset policy
// May be overridden by commandArgs argument parsing
Verilated::randReset(2);
// Before any evaluation, need to know to calculate those signals only used
// for tracing
Verilated::traceEverOn(true);
// Pass arguments so Verilated code can see them, e.g. $value$plusargs
// This needs to be called before you create any model
Verilated::commandArgs(argc, argv);
// General logfile
std::ios::sync_with_stdio();
// Create model
Vtb tb("Vtb");
// You must do one evaluation before enabling waves, in order to allow
// SystemC to interconnect everything for testing.
sc_start(SC_ZERO_TIME);
// If verilator was invoked with --trace argument,
// and if at run time passed the +trace argument, turn on tracing
VerilatedFstSc *tfp = nullptr;
const char *flag = Verilated::commandArgsPlusMatch("trace");
if (flag && 0 == std::strcmp(flag, "+trace")) {
std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
tfp = new VerilatedFstSc;
tb.trace(tfp, 99); // Trace 99 levels of hierarchy
Verilated::mkdir("logs");
tfp->open("logs/vlt_dump.fst");
}
while (!Verilated::gotFinish()) {
// Flush the wave files each cycle so we can immediately see the output
// Don't do this in "real" programs, do it in an abort() handler instead
if (tfp)
tfp->flush();
// Simulate 1ns
sc_start(1, SC_NS);
}
// Final model cleanup
tb.final();
// Close trace if opened
if (tfp) {
tfp->close();
tfp = nullptr;
}
// Return good completion status
return 0;
}

98
src/modules_tb/windows_tb.cpp Normal file
View File

@ -0,0 +1,98 @@
// For read and write
#include <array>
#include <cstdint>
#include <cstdio>
#include <cstdlib>
#include <fstream>
#include <ios>
#include <iostream>
#include <vector>
// SystemC global header
#include "sysc/communication/sc_clock.h"
#include "sysc/communication/sc_signal.h"
#include "sysc/communication/sc_signal_ifs.h"
#include "sysc/kernel/sc_module.h"
#include <memory>
#include <systemc>
// Include common routines
#include "sysc/kernel/sc_time.h"
#include "verilated_fst_sc.h"
#include <sys/stat.h> // mkdir
#include <utility>
#include <verilated.h>
// Include model
#include "VWindows_tb.h"
using namespace sc_core;
using namespace sc_dt;
int sc_main(int argc, char *argv[]) {
std::cout << "Enter into sc_main\n";
// Create logs/ directory in case we have traces to put under it
Verilated::mkdir("logs");
// Set debug level, 0 is off, 9 is highest presently used
// May be overridden by commandArgs argument parsing
Verilated::debug(0);
// Randomization reset policy
// May be overridden by commandArgs argument parsing
Verilated::randReset(2);
// Before any evaluation, need to know to calculate those signals only used
// for tracing
Verilated::traceEverOn(true);
// Pass arguments so Verilated code can see them, e.g. $value$plusargs
// This needs to be called before you create any model
Verilated::commandArgs(argc, argv);
// Create model
VWindows_tb tb("VWindows_tb");
// General logfile
std::ios::sync_with_stdio();
// You must do one evaluation before enabling waves, in order to allow
// SystemC to interconnect everything for testing.
sc_start(SC_ZERO_TIME);
// If verilator was invoked with --trace argument,
// and if at run time passed the +trace argument, turn on tracing
VerilatedFstSc *tfp = nullptr;
const char *flag = Verilated::commandArgsPlusMatch("trace");
if (flag && 0 == std::strcmp(flag, "+trace")) {
std::cout << "Enabling waves into logs/VWindows_tb.fst\n";
tfp = new VerilatedFstSc;
tb.trace(tfp, 99); // Trace 99 levels of hierarchy
Verilated::mkdir("logs");
tfp->open("logs/VWindows_tb.fst");
}
while (!Verilated::gotFinish()) {
// Flush the wave files each cycle so we can immediately see the output
// Don't do this in "real" programs, do it in an abort() handler instead
if (tfp)
tfp->flush();
// Simulate 1ns
sc_start(1, SC_NS);
}
// Final model cleanup
tb.final();
// Close trace if opened
if (tfp) {
tfp->close();
tfp = nullptr;
}
// Return good completion status
return 0;
}

80
src/sc_main_pipeline.cpp
View File

@ -1,26 +1,27 @@
// For read and write // For read and write
#include <array>
#include <cstdint> #include <cstdint>
#include <cstdio> #include <cstdio>
#include <cstdlib> #include <cstdlib>
#include <fstream> #include <fstream>
#include <ios> #include <ios>
#include <iostream> #include <iostream>
#include <vector>
// SystemC global header // SystemC global header
#include "spdlog/common.h" #include "sysc/communication/sc_clock.h"
#include "spdlog/logger.h"
#include "spdlog/sinks/basic_file_sink.h"
#include "sysc/communication/sc_signal.h" #include "sysc/communication/sc_signal.h"
#include "sysc/communication/sc_signal_ifs.h"
#include "sysc/kernel/sc_module.h" #include "sysc/kernel/sc_module.h"
#include <memory> #include <memory>
#include <systemc> #include <systemc>
// Include common routines // Include common routines
#include "sysc/kernel/sc_time.h"
#include "verilated_fst_sc.h"
#include <sys/stat.h> // mkdir #include <sys/stat.h> // mkdir
#include <utility> #include <utility>
#include <vector>
#include <verilated.h> #include <verilated.h>
#include <verilated_vcd_sc.h>
// Include model header, generated from Verilating "isp.v" // Include model header, generated from Verilating "isp.v"
#include "Visp_Pipeline.h" #include "Visp_Pipeline.h"
@ -29,17 +30,24 @@
#include "tb_isp.hpp" #include "tb_isp.hpp"
// Spdlog library // Spdlog library
#include "spdlog/common.h"
#include "spdlog/logger.h"
#include "spdlog/sinks/basic_file_sink.h"
#include "spdlog/sinks/stdout_color_sinks.h" #include "spdlog/sinks/stdout_color_sinks.h"
#include "spdlog/spdlog.h" #include "spdlog/spdlog.h"
#include "verilated_vcd_sc.h"
// Image Parameters // Image Parameters
static const uint16_t IMG_WIDTH = 1936;
static const uint16_t IMG_HEIGHT = 1088;
static const uint32_t IMG_SIZE = (IMG_WIDTH * IMG_HEIGHT);
static const uint16_t IN_WIDTH = 1936; static const uint16_t IN_WIDTH = 1936;
static const uint16_t IN_HEIGHT = 1088; static const uint16_t IN_HEIGHT = 1088;
static const uint32_t IN_SIZE = (IN_WIDTH * IN_HEIGHT); static const uint32_t IN_SIZE = (IN_WIDTH * IN_HEIGHT);
static const uint16_t OUT_WIDTH = 1920; static const uint16_t OUT_WIDTH = 1920;
static const uint16_t OUT_HEIGHT = 1080; static const uint16_t OUT_HEIGHT = 1080;
static const uint32_t OUT_SIZE = (OUT_WIDTH * OUT_HEIGHT); static const uint32_t OUT_SIZE = (OUT_WIDTH * OUT_HEIGHT);
static const uint32_t FLAMES = 2; static const uint32_t FLAMES = 3;
// Input image path and Output directory path // Input image path and Output directory path
#ifndef INPUT_IMG #ifndef INPUT_IMG
@ -54,7 +62,7 @@ struct color_gain {
double red; double red;
double green; double green;
double blue; double blue;
} color_gain{2, 1, 1}, white_gain; } color_gain{1, 1, 1}, white_gain;
static const double gamma_value = 2.2; static const double gamma_value = 2.2;
static const double sat_inc = 0.5; static const double sat_inc = 0.5;
@ -95,13 +103,13 @@ int sc_main(int argc, char *argv[]) {
} }
// Read and Transform Image // Read and Transform Image
std::vector<uint16_t> in_image(IN_SIZE); std::array<uint16_t, IMG_SIZE> in_image;
uint8_t *buf = new uint8_t[2 * IN_SIZE]; uint8_t *buf = new uint8_t[2 * IMG_SIZE];
image.read((char *)buf, 2 * IN_SIZE); image.read((char *)buf, 2 * IMG_SIZE);
uint32_t i = 0; uint32_t i = 0;
for (int y = 0; y < IN_HEIGHT; y++) { for (int y = 0; y < IMG_HEIGHT; y++) {
for (int x = 0; x < IN_WIDTH; x++) { for (int x = 0; x < IMG_WIDTH; x++) {
in_image[y * IN_WIDTH + x] = in_image[y * IMG_WIDTH + x] =
(uint16_t)buf[i] + ((uint16_t)buf[i + 1] << 8); (uint16_t)buf[i] + ((uint16_t)buf[i + 1] << 8);
i += 2; i += 2;
} }
@ -109,6 +117,10 @@ int sc_main(int argc, char *argv[]) {
// Close and delete image // Close and delete image
image.close(); image.close();
delete[] buf; delete[] buf;
// Generate a block number
// std::array<uint16_t, IMG_SIZE> in_image;
// for(int i = 0; i < IMG_SIZE; ++i) in_image[i] = i;
spdlog::info("Finish Reading Image"); spdlog::info("Finish Reading Image");
// This is a more complicated example, please also see the simpler // This is a more complicated example, please also see the simpler
@ -137,19 +149,23 @@ int sc_main(int argc, char *argv[]) {
std::ios::sync_with_stdio(); std::ios::sync_with_stdio();
// Define clocks // Define clocks
sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true}; sc_clock isp_clk{"isp_clk", 10, SC_NS, 0.5, 5, SC_NS, true};
sc_clock camer_clk{"camera_clk", 20, SC_NS, 0.5, 5, SC_NS, true};
// Define interconnect // Define interconnect
sc_signal<bool> rst; sc_signal<bool> rst;
// ISP Modules in ports // ISP Modules in ports
sc_signal<bool> in_valid; sc_signal<bool> in_valid;
sc_signal<bool> in_ready; sc_signal<bool> in_ready;
sc_signal<uint32_t> in_data; sc_signal<uint32_t> in_data;
sc_signal<bool> in_hsync;
sc_signal<bool> in_fsync;
// ISP Modules out ports // ISP Modules out ports
sc_signal<bool> out_valid; sc_signal<bool> out_valid;
sc_signal<bool> out_ready; sc_signal<bool> out_ready;
sc_signal<uint32_t> out_data; sc_signal<uint32_t> out_data;
sc_signal<bool> out_hsync; sc_signal<uint32_t> out_user;
sc_signal<bool> out_fsync; sc_signal<bool> fifo_isp_adapter_h_pixel_correct;
sc_signal<bool> fifo_isp_adapter_v_pixel_correct;
// ISP Modules Enable Ports // ISP Modules Enable Ports
sc_signal<bool> blender_enable; sc_signal<bool> blender_enable;
sc_signal<bool> gamma_enable; sc_signal<bool> gamma_enable;
@ -166,39 +182,51 @@ int sc_main(int argc, char *argv[]) {
// Construct the Verilated model, from inside Visp.h // Construct the Verilated model, from inside Visp.h
Visp_Pipeline isp("Visp"); Visp_Pipeline isp("Visp");
isp.clk(clk); isp.isp_clk(isp_clk);
isp.camera_clk(camer_clk);
isp.reset(rst); isp.reset(rst);
// Connect input signal // Connect input signal
isp.in_valid(in_valid); isp.in_valid(in_valid);
isp.in_ready(in_ready); isp.in_ready(in_ready);
isp.in_data(in_data); isp.in_data(in_data);
isp.in_hsync(in_hsync);
isp.in_fsync(in_fsync);
// Connect output signal // Connect output signal
isp.out_valid(out_valid); isp.out_valid(out_valid);
isp.out_ready(out_ready); isp.out_ready(out_ready);
isp.out_data(out_data); isp.out_data(out_data);
isp.hsync(out_hsync); isp.out_user(out_user);
isp.fsync(out_fsync); isp.fifo_isp_adapter_h_pixel_correct(fifo_isp_adapter_h_pixel_correct);
isp.fifo_isp_adapter_v_pixel_correct(fifo_isp_adapter_v_pixel_correct);
// ISP Settings
// Connect ISP modules enable signal // Connect ISP modules enable signal
isp.blender_enable(blender_enable); isp.blender_enable(blender_enable);
// isp.gamma_enable(gamma_enable);
// Connect ISP modules configuration signal // Connect ISP modules configuration signal
isp.gain_red(gain_red); isp.gain_red(gain_red);
isp.gain_green(gain_green); isp.gain_green(gain_green);
isp.gain_blue(gain_blue); isp.gain_blue(gain_blue);
// for (int i = 0; i < 256; ++i)
// isp.Gtable[i](gamma_table[i]);
// Construct testbench module // Construct testbench module
TB_ISP tb_isp("tb_isp", IN_WIDTH, IN_HEIGHT, OUT_WIDTH, OUT_HEIGHT, FLAMES, TB_ISP tb_isp("tb_isp", IMG_WIDTH, IMG_HEIGHT, IN_WIDTH, IN_HEIGHT, OUT_WIDTH,
OUTPUT_DIR); OUT_HEIGHT, FLAMES, OUTPUT_DIR);
tb_isp.image = std::move(in_image); tb_isp.image = in_image.data();
tb_isp.clk(clk); tb_isp.write_clk(camer_clk);
tb_isp.read_clk(isp_clk);
tb_isp.rst(rst); tb_isp.rst(rst);
// Connect input signal // Connect input signal
tb_isp.in_valid(out_valid); tb_isp.in_valid(out_valid);
tb_isp.in_ready(out_ready); tb_isp.in_ready(out_ready);
tb_isp.in_data(out_data); tb_isp.in_data(out_data);
tb_isp.in_user(out_user);
// Connect output signal // Connect output signal
tb_isp.out_valid(in_valid); tb_isp.out_valid(in_valid);
tb_isp.out_ready(in_ready); tb_isp.out_ready(in_ready);
tb_isp.out_data(in_data); tb_isp.out_data(in_data);
tb_isp.out_hsync(in_hsync);
tb_isp.out_fsync(in_fsync);
// Set ISP modules parameters // Set ISP modules parameters
// Color Blender // Color Blender
@ -229,15 +257,15 @@ int sc_main(int argc, char *argv[]) {
// If verilator was invoked with --trace argument, // If verilator was invoked with --trace argument,
// and if at run time passed the +trace argument, turn on tracing // and if at run time passed the +trace argument, turn on tracing
VerilatedVcdSc *tfp = nullptr; VerilatedFstSc *tfp = nullptr;
const char *flag = Verilated::commandArgsPlusMatch("trace"); const char *flag = Verilated::commandArgsPlusMatch("trace");
if (flag && 0 == std::strcmp(flag, "+trace")) { if (flag && 0 == std::strcmp(flag, "+trace")) {
spdlog::info("Enabling waves into logs/vlt_dump.vcd..."); spdlog::info("Enabling waves into logs/vlt_dump.vcd...");
tfp = new VerilatedVcdSc; tfp = new VerilatedFstSc;
isp.trace(tfp, 99); // Trace 99 levels of hierarchy isp.trace(tfp, 99); // Trace 99 levels of hierarchy
Verilated::mkdir("logs"); Verilated::mkdir("logs");
tfp->open("logs/vlt_dump.vcd"); tfp->open("logs/vlt_dump.fst");
} }
// Simulate until $finish // Simulate until $finish

115
src/tb_isp.hpp
View File

@ -2,6 +2,7 @@
#define __TB_ISP_H__ #define __TB_ISP_H__
#include <cstdint> #include <cstdint>
#include <cstdlib>
#include <iostream> #include <iostream>
#include <memory> #include <memory>
#include <sys/types.h> #include <sys/types.h>
@ -15,6 +16,8 @@
#include "spdlog/sinks/basic_file_sink.h" #include "spdlog/sinks/basic_file_sink.h"
#include "spdlog/sinks/stdout_color_sinks.h" #include "spdlog/sinks/stdout_color_sinks.h"
#include "spdlog/spdlog.h" #include "spdlog/spdlog.h"
#include "sysc/communication/sc_clock_ports.h"
#include "sysc/communication/sc_signal_ports.h"
SC_MODULE(TB_ISP) { SC_MODULE(TB_ISP) {
@ -23,7 +26,8 @@ private:
spdlog::logger img_log; spdlog::logger img_log;
public: public:
sc_core::sc_in_clk clk; sc_core::sc_in_clk read_clk;
sc_core::sc_in_clk write_clk;
sc_core::sc_in<bool> rst; sc_core::sc_in<bool> rst;
sc_core::sc_in<bool> in_ready; // next module ready to receive data sc_core::sc_in<bool> in_ready; // next module ready to receive data
@ -34,6 +38,14 @@ public:
sc_core::sc_out<bool> out_ready; // this module ready to receive data sc_core::sc_out<bool> out_ready; // this module ready to receive data
sc_core::sc_in<uint32_t> in_data; // this module receive data sc_core::sc_in<uint32_t> in_data; // this module receive data
sc_core::sc_out<bool> out_hsync;
sc_core::sc_out<bool> out_fsync;
sc_core::sc_in<uint32_t> in_user;
const uint16_t IMG_WIDTH;
const uint16_t IMG_HEIGHT;
const uint32_t IMG_SIZE;
const uint16_t IN_WIDTH; const uint16_t IN_WIDTH;
const uint16_t IN_HEIGHT; const uint16_t IN_HEIGHT;
const uint32_t IN_SIZE; const uint32_t IN_SIZE;
@ -44,17 +56,19 @@ public:
const std::string OUT_DIR; const std::string OUT_DIR;
bool is_done; // when receive all data bool is_done; // when receive all data
std::vector<uint16_t> image; // the data of image uint16_t *image; // the data of image
std::vector<uint32_t> process_image; // after isp process, the data of image uint32_t *process_image; // image after process
SC_CTOR(TB_ISP, const uint16_t in_width, const uint16_t in_height, SC_CTOR(TB_ISP, const uint16_t img_width, const uint16_t img_height,
const uint16_t in_width, const uint16_t in_height,
const uint16_t out_width, const uint16_t out_height, const uint16_t out_width, const uint16_t out_height,
const uint32_t cnt_flame, const std::string &out_dir) const uint32_t cnt_flame, const std::string &out_dir)
// Init class varibles // Init class varibles
: IN_WIDTH(in_width), IN_HEIGHT(in_height), IN_SIZE(in_width * in_height), : IMG_WIDTH(img_width), IMG_HEIGHT(img_height),
IMG_SIZE(img_width * img_height), IN_WIDTH(in_width),
IN_HEIGHT(in_height), IN_SIZE(in_width * in_height),
OUT_WIDTH(out_width), OUT_HEIGHT(out_height), OUT_WIDTH(out_width), OUT_HEIGHT(out_height),
OUT_SIZE(out_width * out_height), FLAMES(cnt_flame), OUT_DIR(out_dir), OUT_SIZE(out_width * out_height), FLAMES(cnt_flame), OUT_DIR(out_dir),
process_image(std::vector<uint32_t>(out_width * out_height, 0)),
// Global logger with file and stdout // Global logger with file and stdout
log("TB_ISP", log("TB_ISP",
spdlog::sinks_init_list( spdlog::sinks_init_list(
@ -69,47 +83,66 @@ public:
log.set_level(spdlog::level::debug); log.set_level(spdlog::level::debug);
img_log.set_level(spdlog::level::debug); img_log.set_level(spdlog::level::debug);
#endif // DEBUG #endif // DEBUG
process_image = new uint32_t[OUT_SIZE];
SC_CTHREAD(sendData, clk.pos()); // when clk posedge, exec sendData SC_CTHREAD(sendData, write_clk.pos()); // when clk posedge, exec sendData
reset_signal_is(rst, true); // set rst signal reset_signal_is(rst, true); // set rst signal
SC_CTHREAD(readData, clk.pos()); SC_CTHREAD(readData, read_clk.pos());
reset_signal_is(rst, true); // set rst signal reset_signal_is(rst, true); // set rst signal
log.info("Created TB_ISP Modules"); log.info("Created TB_ISP Modules");
} }
~TB_ISP() { delete[] process_image; }
void sendData(void) { void sendData(void) {
// init var // init var
uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0; uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0, data = 0;
bool is_finish = false; // when send all data
// reset // reset
out_valid = false; out_valid = false;
out_fsync = false;
out_hsync = false;
out_data = 0; out_data = 0;
// generate fsync
out_fsync = true;
for (int i = std::rand() % 10 + 1; i > 0; --i)
wait();
out_fsync = false;
while (true) { while (true) {
if (in_ready && !is_finish) { if (in_ready) {
if (pos_x < IN_WIDTH && pos_y < IN_HEIGHT) {
// valid and send data // valid and send data
out_valid = true; out_valid = true;
out_data = image[(pos_y + 0) * IN_WIDTH + pos_x]; out_hsync = true;
data = image[(pos_y + 0) * IMG_WIDTH + pos_x];
out_data = data;
// print data // print data
log.debug("x={:4d}, y={:4d}, data=0x{:04x}", pos_x, pos_y, log.debug("flame={:2d}, x={:4d}, y={:4d}, data=0x{:04x}", cnt_flame,
image[pos_y * IN_WIDTH + pos_x]); pos_x, pos_y, data);
pos_x++; pos_x++;
// calculate position and recognize when to finish } else {
if (pos_x >= IN_WIDTH) {
pos_x = 0; pos_x = 0;
out_hsync = false;
out_valid = false;
pos_y++; pos_y++;
} }
// calculate position and recognize when to finish
if (pos_y >= IN_HEIGHT) { if (pos_y >= IN_HEIGHT) {
out_fsync = true;
for (int i = std::rand() % 10 + 1; i > 0; --i)
wait();
out_fsync = false;
pos_y = 0; pos_y = 0;
cnt_flame++; cnt_flame++;
} }
if (cnt_flame >= FLAMES + 1) {
is_finish = true;
}
} else { } else {
out_valid = false; out_valid = false;
} }
@ -122,6 +155,7 @@ public:
void readData(void) { void readData(void) {
// init local var // init local var
uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0; uint16_t pos_x = 0, pos_y = 0, cnt_flame = 0;
uint32_t location = 0;
uint32_t last_data = 0, cnt = 0; uint32_t last_data = 0, cnt = 0;
bool is_finish = false; bool is_finish = false;
// reset // reset
@ -132,27 +166,33 @@ public:
if (!is_finish) { if (!is_finish) {
out_ready = true; out_ready = true;
// when data valid, write it down
if (in_valid) { if (in_valid) {
process_image[pos_y * OUT_WIDTH + pos_x] = in_data;
// calculate position // when fsync valid, save img
pos_x++; if (in_user == 0x03) {
if (pos_x >= OUT_WIDTH) {
pos_x = 0; pos_x = 0;
pos_y++;
}
if (pos_y >= OUT_HEIGHT) {
pos_y = 0; pos_y = 0;
saveData( saveData(
("output_img_" + std::to_string(cnt_flame) + ".bmp").c_str()); ("output_img_" + std::to_string(cnt_flame) + ".bmp").c_str());
cnt_flame++; cnt_flame++;
}
if (cnt_flame >= FLAMES) { if (cnt_flame >= FLAMES) {
is_finish = true; is_finish = true;
} }
} }
location = pos_y * OUT_WIDTH + pos_x;
process_image[location] = in_data;
img_log.info("Flame {:d}: Receive {:d} pixels\tWait {:d} pixels",
cnt_flame, location, OUT_SIZE - location);
// calculate position
pos_x++;
if (pos_x >= OUT_WIDTH) {
pos_x = 0;
pos_y++;
}
}
} else { } else {
out_ready = false; out_ready = false;
} }
@ -178,12 +218,6 @@ public:
bool saveData(const char *name) { bool saveData(const char *name) {
bool ret = true; bool ret = true;
// Check Image Size
if (process_image.size() > OUT_SIZE) {
log.error("Image Over Size!!!\nImage Size:{:d}", process_image.size());
return false;
}
// Write BMP image // Write BMP image
bitmap_image bmp(OUT_WIDTH, OUT_HEIGHT); bitmap_image bmp(OUT_WIDTH, OUT_HEIGHT);
if (!bmp) { if (!bmp) {
@ -191,15 +225,14 @@ public:
return false; return false;
} }
img_log.info("Image Receive: {:d} Pixels, {:d} Bytes", process_image.size(),
process_image.size() * 3);
unsigned char red = 0, green = 0, blue = 0; unsigned char red = 0, green = 0, blue = 0;
uint32_t data = 0;
for (int y = 0; y < OUT_HEIGHT; y++) { for (int y = 0; y < OUT_HEIGHT; y++) {
for (int x = 0; x < OUT_WIDTH; x++) { for (int x = 0; x < OUT_WIDTH; x++) {
red = (process_image[y * OUT_WIDTH + x] & 0x00ff0000) >> 16; data = process_image[y * OUT_WIDTH + x];
green = (process_image[y * OUT_WIDTH + x] & 0x0000ff00) >> 8; red = (data & 0x00ff0000) >> 16;
blue = (process_image[y * OUT_WIDTH + x] & 0x000000ff) >> 0; green = (data & 0x0000ff00) >> 8;
blue = (data & 0x000000ff) >> 0;
img_log.debug( img_log.debug(
"x={:4d}, y={:4d}, red=0x{:02x}, green=0x{:02x}, blue=0x{:02x}", x, "x={:4d}, y={:4d}, red=0x{:02x}, green=0x{:02x}, blue=0x{:02x}", x,
y, red, green, blue); y, red, green, blue);

1
xmake.lua
View File

@ -18,6 +18,7 @@ target("TB_ISP")
"src", "src",
"build/CMakeFiles/Visp_Pipeline.dir/Visp_Pipeline.dir", "build/CMakeFiles/Visp_Pipeline.dir/Visp_Pipeline.dir",
"build/CMakeFiles/Visp.dir/Visp.dir", "build/CMakeFiles/Visp.dir/Visp.dir",
"build/CMakeFiles/VWindows.dir/VWindows_tb.dir",
"src/img_process", "src/img_process",
INCLUDE_DIRS INCLUDE_DIRS
) )