118 lines
3.6 KiB
Systemverilog
118 lines
3.6 KiB
Systemverilog
module Crop_Pipeline #(
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parameter IN_WIDTH = 512,
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parameter IN_HEIGHT = 512,
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parameter OFFSET_X = 120,
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parameter OFFSET_Y = 256,
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// parameter TRANSLAYT_X = 120,
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// parameter TRANSLAYT_Y = 120,
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parameter OUT_WIDTH = 512,
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parameter OUT_HEIGHT = 512,
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parameter BLANK_COLOR = 6'h000000,
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parameter COLOR_DEPTH = 16
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) (
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input wire clk,
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input wire reset,
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input wire [COLOR_DEPTH - 1:0] in_data [3],
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input wire [7:0] in_user,
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output reg [COLOR_DEPTH - 1:0] out_data [3],
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output wire [7:0] out_user,
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input wire in_valid,
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output reg out_valid,
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input wire in_ready,
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output wire out_ready
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);
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wire in_fstart, in_hstart;
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reg out_fstart, out_hstart;
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assign in_fstart = in_user[1];
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assign in_hstart = in_user[0];
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localparam PIPELINE = 3;
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reg [5:0] pipeline_user[PIPELINE];
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reg [PIPELINE-1:0] pipeline_valid;
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wire pipeline_running;
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assign pipeline_running = in_ready | ~pipeline_valid[PIPELINE-1];
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reg [31:0] cnt_x, cnt_y, temp_x, temp_y;
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reg force_dis;
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reg [COLOR_DEPTH-1:0] data_cache0[3];
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reg [COLOR_DEPTH-1:0] data_cache1[3];
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//out_ready ：只要本模块可以接收数据就一直拉高
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assign out_ready = pipeline_running;
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//out_valid ：只要本模块可以发出数据就一直拉高
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assign out_valid = (pipeline_valid[PIPELINE-1] & ~force_dis);
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assign out_user = {pipeline_user[PIPELINE-1],out_fstart,out_hstart};
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//分别表示当前像素: 显示；被裁掉；空。
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reg flag_crop;
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localparam CROP_KEEP = 1'b0,
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CROP_GIVE_UP = 1'b1;
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integer i;
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always @(posedge clk) begin
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if(reset) for(i=0;i<3;i=i+1) data_cache0[i] <= 0;
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else if(pipeline_running & in_valid) for(i=0;i<3;i++) data_cache0[i] <= in_data[i];
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else for(i=0;i<3;i=i+1) data_cache0[i] <= data_cache0[i];
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end
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always @(posedge clk) begin
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if(reset) for(i=0;i<3;i=i+1) data_cache1[i] <= 0;
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else if(pipeline_running & pipeline_valid[0]) for(i=0;i<3;i++) data_cache1[i] <= data_cache0[i];
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else for(i=0;i<3;i=i+1) data_cache1[i] <= data_cache1[i];
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end
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always @(posedge clk) begin
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if(reset) begin
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pipeline_valid <= 0;
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cnt_x <= 0;
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cnt_y <= 0;
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for(i=0;i<3;i=i+1) out_data[i] <= 0;
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flag_crop <= 0;
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force_dis <= 0;
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out_hstart <= 0;
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out_fstart <= 0;
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temp_x <= 0;
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temp_y <= 0;
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for(i=0;i<PIPELINE;i=i+1) pipeline_user[i] <= 0;
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end else if(pipeline_running) begin
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pipeline_valid <= {pipeline_valid[PIPELINE-2:0],in_valid};
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if(in_valid) begin //when 00
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pipeline_user[0] <= in_user[7:2];
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cnt_x <= (in_hstart)?(0):(cnt_x+1);
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cnt_y <= (in_hstart)?((in_fstart)?(0):(cnt_y+1)):(cnt_y);
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end
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if(pipeline_valid[0]) begin //when 00
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pipeline_user[1] <= pipeline_user[0];
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temp_x <= cnt_x;
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temp_y <= cnt_y;
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if(cnt_x < OFFSET_X || cnt_y < OFFSET_Y) flag_crop <= CROP_GIVE_UP;
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else if(cnt_x < OFFSET_X + OUT_WIDTH && cnt_y < OFFSET_Y + OUT_HEIGHT) flag_crop <= CROP_KEEP;
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else flag_crop <= CROP_GIVE_UP;
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end
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if(pipeline_valid[1]) begin
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pipeline_user[2] <= pipeline_user[1];
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for(i=0;i<3;i++) out_data[i] <= data_cache1[i];
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out_hstart <= (temp_x == OFFSET_X) && (temp_y >= OFFSET_Y);
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out_fstart <= (temp_x == OFFSET_X) && (temp_y == OFFSET_Y);
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case (flag_crop)
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CROP_KEEP : force_dis <= 1'b0;
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CROP_GIVE_UP : force_dis <= 1'b1;
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endcase
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end
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end
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end
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endmodule
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