306 lines
13 KiB
Systemverilog
306 lines
13 KiB
Systemverilog
module DPC #(
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parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
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parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
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parameter reg signed [15:0] THRESHOLD = 30, // 阈值
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parameter reg [ 4:0] MODULE_ENABLE = 0, // 是否启用该模块，DEBUG用
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parameter reg [ 4:0] LABLE_ENABLE= 1 // 0:不启用标注, 1:启用标注, 2:启用方向标注
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)(
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input wire clk,
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input wire reset,
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input wire [DATA_WIDTH - 1:0] in_data [5*5],
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input wire [7:0] in_user,
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output reg [DATA_WIDTH - 1:0] out_data,
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output wire [7:0] out_user,
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input wire in_valid,
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output wire out_valid,
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input wire in_ready,
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output wire out_ready
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);
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localparam WINDOW_LENGTH = 5;
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localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH;
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localparam EXPAND_BITS = 1;
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localparam PIPILINE = 9;
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reg [7:0] pipeline_user[PIPILINE];
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reg [PIPILINE-1:0] pipeline_valid;
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wire pipeline_running;
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assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
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//out_ready ：只要本模块可以接收数据就一直拉高
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assign out_ready = pipeline_running;
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//out_valid ：只要本模块可以发出数据就一直拉高
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assign out_valid = pipeline_valid[PIPILINE-1];
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assign out_user = pipeline_user[PIPILINE-1];
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache[9]; // 缓存颜色通道数据，channel_cache[4]就是中心像素点
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache0,channel_cache1,channel_cache2,channel_cache3,channel_cache4; // 缓存中心像素点的颜色数据
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache[3], grad_v_cache[3], grad_i_cache[3], grad_t_cache[3];
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache0[3], grad_v_cache0[3], grad_i_cache0[3], grad_t_cache0[3];
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache1[3], grad_v_cache1[3], grad_i_cache1[3], grad_t_cache1[3];
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reg signed [DATA_WIDTH-1+EXPAND_BITS+2:0] grad_cache_excute[4];
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_cache_center[4];
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache_correct[4], channel_cache_correct1[4], channel_cache_correct2[4];
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reg signed [DATA_WIDTH-1+EXPAND_BITS+EXPAND_BITS:0] channel_cache_correct0[4];
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reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_median_cache[4];
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reg [1:0] flag_which_dict, dic2;
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reg [DATA_WIDTH-1:0] channel_cache_correct_final;
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reg flag_if_need_corection;
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reg pos_x, pos_y;
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reg [1:0] raw_type;
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/*
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-------h
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|\ i
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| \/
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| /\
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|/ \
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v t
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*/
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integer i;
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always @(posedge clk) begin
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if(reset) begin
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for(i=0;i<PIPILINE;i=i+1) pipeline_user[i] <= 0;
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for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= 0;
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for(i=0;i<DATA_NUM;i=i+1) data_cache0[i] <= 0;
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for(i=0;i<9;i=i+1) channel_cache[i] <= 0;
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channel_cache0 <= 0;
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channel_cache1 <= 0;
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channel_cache2 <= 0;
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channel_cache3 <= 0;
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channel_cache4 <= 0;
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channel_cache_correct_final <= 0;
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for(i=0;i<3;i=i+1) grad_h_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_h_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_h_cache1[i] <= 0; for(i=0;i<3;i=i+1);
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for(i=0;i<3;i=i+1) grad_v_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_v_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_v_cache1[i] <= 0; for(i=0;i<3;i=i+1);
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for(i=0;i<3;i=i+1) grad_i_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_i_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_i_cache1[i] <= 0; for(i=0;i<3;i=i+1);
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for(i=0;i<3;i=i+1) grad_t_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_t_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_t_cache1[i] <= 0; for(i=0;i<3;i=i+1);
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for(i=0;i<3;i=i+1) grad_median_cache[i] <= 0;
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for(i=0;i<4;i=i+1) grad_cache_excute[i] <= 0;
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for(i=0;i<4;i=i+1) grad_cache_center[i] <= 0;
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flag_which_dict <= 0;
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flag_if_need_corection <= 0;
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for(i=0;i<4;i=i+1) channel_cache_correct[i] <= 0; for(i=0;i<4;i=i+1) channel_cache_correct1[i] <= 0;
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for(i=0;i<4;i=i+1) channel_cache_correct0[i] <= 0;for(i=0;i<4;i=i+1) channel_cache_correct2[i] <= 0;
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pipeline_valid <= 0;
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out_data <= 0;
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pos_x <= 0;
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pos_y <= 0;
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raw_type <= RAW_TYPE;
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end else if(pipeline_running) begin
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pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
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if(in_valid) begin
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for(i=0;i<DATA_NUM;i=i+1) data_cache0[i] <= {{(EXPAND_BITS){1'b0}},in_data[i]};
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pipeline_user[0] <= in_user;
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pos_x <= (in_user[0])?(0):(~pos_x);
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pos_y <= (in_user[0])?((in_user[1])?(0):(~pos_y)):(pos_y);
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end
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if(pipeline_valid[0]) begin
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for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= data_cache0[i];
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pipeline_user[1] <= pipeline_user[0];
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case (RAW_TYPE)
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2'b00: raw_type <= { pos_y, pos_x};
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2'b01: raw_type <= { pos_y, ~pos_x};
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2'b10: raw_type <= {~pos_y, pos_x};
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2'b11: raw_type <= {~pos_y, ~pos_x};
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endcase
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end
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if(pipeline_valid[1]) begin
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pipeline_user[2] <= pipeline_user[1];
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case (raw_type)
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1,2: begin
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channel_cache[0] <= data_cache[00];
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channel_cache[1] <= data_cache[10];
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channel_cache[2] <= data_cache[20];
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channel_cache[3] <= data_cache[02];
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channel_cache[4] <= data_cache[12];
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channel_cache[5] <= data_cache[22];
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channel_cache[6] <= data_cache[04];
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channel_cache[7] <= data_cache[14];
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channel_cache[8] <= data_cache[24];
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end
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0,3: begin
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channel_cache[0] <= data_cache[02];
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channel_cache[1] <= data_cache[06];
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channel_cache[2] <= data_cache[10];
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channel_cache[3] <= data_cache[08];
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channel_cache[4] <= data_cache[12];
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channel_cache[5] <= data_cache[16];
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channel_cache[6] <= data_cache[14];
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channel_cache[7] <= data_cache[18];
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channel_cache[8] <= data_cache[22];
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end
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endcase
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end
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if(pipeline_valid[2]) begin //计算梯度，同时开始校正后数据的部分计算
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pipeline_user[3] <= pipeline_user[2];
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channel_cache0 <= channel_cache[4];
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grad_h_cache[0] <= channel_cache[0]/2 + channel_cache[2]/2 - channel_cache[1];
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grad_h_cache[1] <= channel_cache[3]/2 + channel_cache[5]/2 - channel_cache[4];
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grad_h_cache[2] <= channel_cache[6]/2 + channel_cache[8]/2 - channel_cache[7];
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grad_v_cache[0] <= channel_cache[0]/2 + channel_cache[6]/2 - channel_cache[3];
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grad_v_cache[1] <= channel_cache[1]/2 + channel_cache[7]/2 - channel_cache[4];
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grad_v_cache[2] <= channel_cache[2]/2 + channel_cache[8]/2 - channel_cache[5];
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grad_i_cache[0] <= channel_cache[1]/2 - channel_cache[3]/2;
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grad_i_cache[1] <= channel_cache[6]/2 + channel_cache[2]/2 - channel_cache[4];
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grad_i_cache[2] <= channel_cache[5]/2 - channel_cache[7]/2;
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grad_t_cache[0] <= channel_cache[1]/2 - channel_cache[5]/2;
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grad_t_cache[1] <= channel_cache[0]/2 + channel_cache[8]/2 - channel_cache[4];
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grad_t_cache[2] <= channel_cache[3]/2 - channel_cache[7]/2;
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channel_cache_correct[0] <= channel_cache[3]/2 + channel_cache[5]/2;
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channel_cache_correct[1] <= channel_cache[1]/2 + channel_cache[7]/2;
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channel_cache_correct[2] <= channel_cache[2]/2 + channel_cache[6]/2;
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channel_cache_correct[3] <= channel_cache[0]/2 + channel_cache[8]/2;
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end
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if(pipeline_valid[3]) begin //计算绝对值，同时完成校正后数据的计算
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pipeline_user[4] <= pipeline_user[3];
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channel_cache1 <= channel_cache0;
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for(i=0;i<3;i=i+1) grad_h_cache0[i] <= (grad_h_cache[i] < 0) ? (-grad_h_cache[i]) : (grad_h_cache[i]);
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for(i=0;i<3;i=i+1) grad_v_cache0[i] <= (grad_v_cache[i] < 0) ? (-grad_v_cache[i]) : (grad_v_cache[i]);
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for(i=0;i<3;i=i+1) grad_i_cache0[i] <= (grad_i_cache[i] < 0) ? (-grad_i_cache[i]) : (grad_i_cache[i]);
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for(i=0;i<3;i=i+1) grad_t_cache0[i] <= (grad_t_cache[i] < 0) ? (-grad_t_cache[i]) : (grad_t_cache[i]);
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channel_cache_correct0[0] <= channel_cache_correct[0] - grad_h_cache[0]/2 - grad_h_cache[2]/2;
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channel_cache_correct0[1] <= channel_cache_correct[1] - grad_v_cache[0]/2 - grad_v_cache[2]/2;
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channel_cache_correct0[2] <= channel_cache_correct[2] - grad_i_cache[0]/2 - grad_i_cache[2]/2;
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channel_cache_correct0[3] <= channel_cache_correct[3] - grad_t_cache[0]/2 - grad_t_cache[2]/2;
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end
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if(pipeline_valid[4]) begin //计算中位数
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pipeline_user[5] <= pipeline_user[4];
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channel_cache2 <= channel_cache1;
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for(i=0;i<4;i=i+1) channel_cache_correct1[i] <= (channel_cache_correct0[i] < 0) ? (0) : (channel_cache_correct0[i]);
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// for(i=0;i<4;i=i+1) channel_cache_correct1[i] <= channel_cache_correct0[i];
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for(i=0;i<3;i=i+1) grad_h_cache1[i] <= grad_h_cache0[i];
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for(i=0;i<3;i=i+1) grad_v_cache1[i] <= grad_v_cache0[i];
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for(i=0;i<3;i=i+1) grad_i_cache1[i] <= grad_i_cache0[i];
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for(i=0;i<3;i=i+1) grad_t_cache1[i] <= grad_t_cache0[i];
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grad_median_cache[0] <= MEDIAN(grad_h_cache0);
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grad_median_cache[1] <= MEDIAN(grad_v_cache0);
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grad_median_cache[2] <= MEDIAN(grad_i_cache0);
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grad_median_cache[3] <= MEDIAN(grad_t_cache0);
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end
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if(pipeline_valid[5]) begin //计算最小值，判断最小梯度方向
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pipeline_user[6] <= pipeline_user[5];
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channel_cache3 <= channel_cache2;
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for(i=0;i<4;i=i+1) channel_cache_correct2[i] <= channel_cache_correct1[i];
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grad_cache_center[0] <= grad_h_cache1[1]/4;
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grad_cache_center[1] <= grad_v_cache1[1]/4;
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grad_cache_center[2] <= grad_i_cache1[1]/4;
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grad_cache_center[3] <= grad_t_cache1[1]/4;
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grad_cache_excute[0] <= grad_h_cache1[0] + grad_h_cache1[2] + THRESHOLD;
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grad_cache_excute[1] <= grad_v_cache1[0] + grad_v_cache1[2] + THRESHOLD;
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grad_cache_excute[2] <= grad_i_cache1[0] + grad_i_cache1[2] + THRESHOLD;
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grad_cache_excute[3] <= grad_t_cache1[0] + grad_t_cache1[2] + THRESHOLD;
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flag_which_dict <= MIN(grad_median_cache);
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end
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if(pipeline_valid[6]) begin //在最小梯度方向上判断中心点是否是坏点
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pipeline_user[7] <= pipeline_user[6];
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dic2 <= flag_which_dict;
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channel_cache4 <= channel_cache3;
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channel_cache_correct_final <= channel_cache_correct2[flag_which_dict][DATA_WIDTH-1:0];
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case (flag_which_dict)
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2'b00, 2'b01: flag_if_need_corection <= (grad_cache_center[flag_which_dict] > grad_cache_excute[flag_which_dict]);
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2'b10, 2'b11: flag_if_need_corection <= (grad_cache_center[2] > grad_cache_excute[2]) && ((grad_cache_center[3] > grad_cache_excute[3]));
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endcase
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end
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if(pipeline_valid[7]) begin //如果是坏点，输出计算后的值；如果不是坏点，输出原值
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// if(flag_if_need_corection == 1'b1 && channel_cache_correct_final == 0) $stop;
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pipeline_user[8] <= pipeline_user[7];
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if(MODULE_ENABLE) begin
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case(LABLE_ENABLE)
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0: out_data <= (flag_if_need_corection)?(channel_cache_correct_final):(channel_cache4);
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1: out_data <= (flag_if_need_corection)?(12'hFFF):(channel_cache4);
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2: begin
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case(dic2)
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2'b00: out_data <= (12'h00F);
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2'b01: out_data <= (12'h0F0);
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2'b10: out_data <= (12'hF00);
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2'b11: out_data <= (12'h0FF);
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endcase
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end
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endcase
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end else out_data <= channel_cache4;
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end
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end
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end
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function signed [DATA_WIDTH-1+EXPAND_BITS:0] MEDIAN;
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input signed [DATA_WIDTH-1+EXPAND_BITS:0] inx[3];
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begin
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if((inx[0] >= inx[1] && inx[1] >= inx[2]) || (inx[2] >= inx[1] && inx[1] >= inx[0])) MEDIAN = inx[1];
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else if((inx[1] >= inx[0] && inx[0] >= inx[2]) || (inx[2] >= inx[0] && inx[0] >= inx[1])) MEDIAN = inx[0];
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else MEDIAN = inx[2];
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end
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endfunction
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function [1:0] MIN;
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input signed [DATA_WIDTH-1+EXPAND_BITS:0] inx[4];
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begin
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if(inx[0] <= inx[1] && inx[0] <= inx[2] && inx[0] <= inx[3]) MIN = 2'b00;
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else if(inx[1] <= inx[2] && inx[1] <= inx[3]) MIN = 2'b01;
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else if(inx[2] <= inx[3]) MIN = 2'b10;
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else MIN = 2'b11;
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end
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endfunction
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/*
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00 05 10 15 20
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01 06 11 16 21 0 1 2
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02 07 12 17 22 -> 3 4 5
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03 08 13 18 23 6 7 8
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04 09 14 19 24
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rawtype==0: center is GREEN
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g r g r g / / g / /
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b g b g b / g / g /
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g r g r g -> g / G / g
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b g b g b / g / g /
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g r g r g / / g / /
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rawtype==1: center is RED
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r g r g r r / r / r
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g b g b g / / / / /
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r g r g r -> r / R / r
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g b g b g / / / / /
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r g r g r r / r / r
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rawtype==2: center is BLUE
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b g b g b b / b / b
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g r g r g / / / / /
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b g b g b -> b / B / b
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g r g r g / / / / /
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b g b g b b / b / b
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rawtype==3: center is GREEN
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g b g b g / / g / /
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r g r g r / g / g /
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g b g b g -> g / G / g
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r g r g r / g / g /
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r g r g r / / g / /
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*/
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endmodule
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