module DPC #( parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值 parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽 parameter reg signed [15:0] THRESHOLD = 30, // 阈值 parameter reg [ 4:0] MODULE_ENABLE = 0, // 是否启用该模块，DEBUG用 parameter reg [ 4:0] LABLE_ENABLE= 1 // 0:不启用标注, 1:启用标注, 2:启用方向标注 )( input wire clk, input wire reset, input wire [DATA_WIDTH - 1:0] in_data [5*5], input wire [7:0] in_user, output reg [DATA_WIDTH - 1:0] out_data, output wire [7:0] out_user, input wire in_valid, output wire out_valid, input wire in_ready, output wire out_ready ); localparam WINDOW_LENGTH = 5; localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH; localparam EXPAND_BITS = 1; localparam PIPILINE = 9; reg [7:0] pipeline_user[PIPILINE]; reg [PIPILINE-1:0] pipeline_valid; wire pipeline_running; assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1]; //out_ready ：只要本模块可以接收数据就一直拉高 assign out_ready = pipeline_running; //out_valid ：只要本模块可以发出数据就一直拉高 assign out_valid = pipeline_valid[PIPILINE-1]; assign out_user = pipeline_user[PIPILINE-1]; reg signed [DATA_WIDTH-1+EXPAND_BITS:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn reg signed [DATA_WIDTH-1+EXPAND_BITS:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache[9]; // 缓存颜色通道数据，channel_cache[4]就是中心像素点 reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache0,channel_cache1,channel_cache2,channel_cache3,channel_cache4; // 缓存中心像素点的颜色数据 reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache[3], grad_v_cache[3], grad_i_cache[3], grad_t_cache[3]; reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache0[3], grad_v_cache0[3], grad_i_cache0[3], grad_t_cache0[3]; reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache1[3], grad_v_cache1[3], grad_i_cache1[3], grad_t_cache1[3]; reg signed [DATA_WIDTH-1+EXPAND_BITS+2:0] grad_cache_excute[4]; reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_cache_center[4]; reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache_correct[4], channel_cache_correct1[4], channel_cache_correct2[4]; reg signed [DATA_WIDTH-1+EXPAND_BITS+EXPAND_BITS:0] channel_cache_correct0[4]; reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_median_cache[4]; reg [1:0] flag_which_dict, dic2; reg [DATA_WIDTH-1:0] channel_cache_correct_final; reg flag_if_need_corection; reg pos_x, pos_y; reg [1:0] raw_type; /* -------h |\ i | \/ | /\ |/ \ v t */ integer i; always @(posedge clk) begin if(reset) begin for(i=0;i grad_cache_excute[flag_which_dict]); 2'b10, 2'b11: flag_if_need_corection <= (grad_cache_center[2] > grad_cache_excute[2]) && ((grad_cache_center[3] > grad_cache_excute[3])); endcase end if(pipeline_valid[7]) begin //如果是坏点，输出计算后的值；如果不是坏点，输出原值 // if(flag_if_need_corection == 1'b1 && channel_cache_correct_final == 0) $stop; pipeline_user[8] <= pipeline_user[7]; if(MODULE_ENABLE) begin case(LABLE_ENABLE) 0: out_data <= (flag_if_need_corection)?(channel_cache_correct_final):(channel_cache4); 1: out_data <= (flag_if_need_corection)?(12'hFFF):(channel_cache4); 2: begin case(dic2) 2'b00: out_data <= (12'h00F); 2'b01: out_data <= (12'h0F0); 2'b10: out_data <= (12'hF00); 2'b11: out_data <= (12'h0FF); endcase end endcase end else out_data <= channel_cache4; end end end function signed [DATA_WIDTH-1+EXPAND_BITS:0] MEDIAN; input signed [DATA_WIDTH-1+EXPAND_BITS:0] inx[3]; begin if((inx[0] >= inx[1] && inx[1] >= inx[2]) || (inx[2] >= inx[1] && inx[1] >= inx[0])) MEDIAN = inx[1]; else if((inx[1] >= inx[0] && inx[0] >= inx[2]) || (inx[2] >= inx[0] && inx[0] >= inx[1])) MEDIAN = inx[0]; else MEDIAN = inx[2]; end endfunction function [1:0] MIN; input signed [DATA_WIDTH-1+EXPAND_BITS:0] inx[4]; begin if(inx[0] <= inx[1] && inx[0] <= inx[2] && inx[0] <= inx[3]) MIN = 2'b00; else if(inx[1] <= inx[2] && inx[1] <= inx[3]) MIN = 2'b01; else if(inx[2] <= inx[3]) MIN = 2'b10; else MIN = 2'b11; end endfunction /* 00 05 10 15 20 01 06 11 16 21 0 1 2 02 07 12 17 22 -> 3 4 5 03 08 13 18 23 6 7 8 04 09 14 19 24 rawtype==0: center is GREEN g r g r g / / g / / b g b g b / g / g / g r g r g -> g / G / g b g b g b / g / g / g r g r g / / g / / rawtype==1: center is RED r g r g r r / r / r g b g b g / / / / / r g r g r -> r / R / r g b g b g / / / / / r g r g r r / r / r rawtype==2: center is BLUE b g b g b b / b / b g r g r g / / / / / b g b g b -> b / B / b g r g r g / / / / / b g b g b b / b / b rawtype==3: center is GREEN g b g b g / / g / / r g r g r / g / g / g b g b g -> g / G / g r g r g r / g / g / r g r g r / / g / / */ endmodule