103 lines
2.6 KiB
Systemverilog
103 lines
2.6 KiB
Systemverilog
//RAM-BASED移位寄存器
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module SHIFT_REGISTER #(
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parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
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parameter IFOUTIMME = 1'b0 //此项为0时，直至RAM存满IMAGE_WIDTH后再输出valid，为1时立即输出valid，无论是否存满
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)(
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// 基本信号
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input wire clk,
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input wire reset,
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// 数据线
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input wire [DATA_WIDTH - 1:0] in_data,
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input wire [7:0] in_user, //in_user[0]是hstart, 行开始标志位, 用于给SHIFT_REGISTER判断输出与输入data的addr距离
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output wire [DATA_WIDTH - 1:0] out_data,
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output wire [7:0] out_user,
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// 有效信号
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input wire in_valid, // 上一模块输出数据有效
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output wire out_valid // 当前模块输出数据有效
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);
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reg [10:0] addr_a, addr_b;
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wire cea, ceb;
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reg fulldone;
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reg in_valid_temp0, in_valid_temp1;
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always @(posedge clk) in_valid_temp0 <= in_valid && (fulldone || IFOUTIMME);
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always @(posedge clk) in_valid_temp1 <= in_valid_temp0;
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assign cea = in_valid;
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assign ceb = in_valid_temp0;
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assign out_valid = in_valid_temp1;
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wire hstart;
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assign hstart = in_user[0];
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reg [15:0] wr_rd_distance_cnt;
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always @(posedge clk) begin
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if(reset) begin
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addr_a <= ~0;
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addr_b <= 0;
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wr_rd_distance_cnt <= 0;
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end else if(cea) begin
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addr_a <= addr_a + 1;
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if(hstart) begin
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wr_rd_distance_cnt <= 0;
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addr_b <= addr_a + 1 - (wr_rd_distance_cnt + 2);
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end else begin
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addr_b <= addr_b + 1;
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wr_rd_distance_cnt <= wr_rd_distance_cnt + 1;
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end
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end else begin
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addr_a <= addr_a;
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addr_b <= addr_b;
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wr_rd_distance_cnt <= wr_rd_distance_cnt;
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end
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end
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always @(posedge clk) begin
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if(reset) fulldone <= 0;
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else if(cea && hstart && (addr_b != 0)) fulldone <= 1;
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else fulldone <= fulldone;
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end
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wire [15:0] din, dout;
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assign din = {{(16-DATA_WIDTH){1'b0}},in_data};
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assign out_data = dout[DATA_WIDTH-1:0];
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// Single-Double-Port-BRAM-IP Bypass Normal
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Gowin_SDPB Gowin_SDPB_inst(
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.clka(clk), //input clka
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.clkb(clk), //input clkb
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.reset(reset), //input reset
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.cea(cea), //input cea
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.ceb(ceb), //input ceb
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.ada(addr_a), //input [10:0] ada
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.adb(addr_b), //input [10:0] adb
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.din(din), //input [15:0] din
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.dout(dout), //output [15:0] dout
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.oce(1) //input oce
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);
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// Single-Double-Port-BRAM-IP Bypass Normal
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Gowin_SDPB_USER Gowin_SDPB_user_inst(
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.clka(clk), //input clka
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.clkb(clk), //input clkb
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.reset(reset), //input reset
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.cea(cea), //input cea
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.ceb(ceb), //input ceb
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.ada(addr_a), //input [10:0] ada
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.adb(addr_b), //input [10:0] adb
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.din(in_user), //input [7:0] din
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.dout(out_user), //output [7:0] dout
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.oce(1) //input oce
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);
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endmodule
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