51 lines
1.3 KiB
Verilog
51 lines
1.3 KiB
Verilog
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
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//All rights reserved.
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//File Title: IP file
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//Tool Version: V1.9.10.02
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//Part Number: GW5AST-LV138FPG676AES
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//Device: GW5AST-138
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//Device Version: B
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//Created Time: Fri Nov 1 11:18:28 2024
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module Gowin_SDPB_USER (dout, clka, cea, clkb, ceb, oce, reset, ada, din, adb);
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output [7:0] dout;
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input clka;
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input cea;
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input clkb;
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input ceb;
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input oce;
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input reset;
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input [10:0] ada;
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input [7:0] din;
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input [10:0] adb;
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wire [23:0] sdpb_inst_0_dout_w;
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wire gw_gnd;
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assign gw_gnd = 1'b0;
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SDPB sdpb_inst_0 (
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.DO({sdpb_inst_0_dout_w[23:0],dout[7:0]}),
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.CLKA(clka),
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.CEA(cea),
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.CLKB(clkb),
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.CEB(ceb),
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.OCE(oce),
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.RESET(reset),
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.BLKSELA({gw_gnd,gw_gnd,gw_gnd}),
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.BLKSELB({gw_gnd,gw_gnd,gw_gnd}),
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.ADA({ada[10:0],gw_gnd,gw_gnd,gw_gnd}),
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.DI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,din[7:0]}),
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.ADB({adb[10:0],gw_gnd,gw_gnd,gw_gnd})
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);
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defparam sdpb_inst_0.READ_MODE = 1'b0;
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defparam sdpb_inst_0.BIT_WIDTH_0 = 8;
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defparam sdpb_inst_0.BIT_WIDTH_1 = 8;
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defparam sdpb_inst_0.BLK_SEL_0 = 3'b000;
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defparam sdpb_inst_0.BLK_SEL_1 = 3'b000;
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defparam sdpb_inst_0.RESET_MODE = "SYNC";
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endmodule //Gowin_SDPB_USER
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