140 lines
5.1 KiB
Systemverilog
140 lines
5.1 KiB
Systemverilog
module Windows #(
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parameter DATA_WIDTH = 16,
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parameter WINDOWS_WIDTH = 3,
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parameter WINDOWS_ANCHOR_X = 1,//禁止大于WINDOWS_WIDTH-1
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parameter WINDOWS_ANCHOR_Y = 1 //禁止大于WINDOWS_WIDTH-1
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)(
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// 基本信号
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input wire clk,
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input wire reset,
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// 数据线
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input wire [DATA_WIDTH - 1:0] in_data,
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input wire [7:0] in_user,
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output reg [DATA_WIDTH - 1:0] out_data [WINDOWS_WIDTH*WINDOWS_WIDTH], // 数据输出线
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output wire [7:0] out_user,
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// 有效信号
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input wire in_valid, // 上一模块输出数据有效
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output wire out_valid, // 当前模块输出数据有效
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// 准备信号 Windows模块无法停止，因此默认不处理准备信号
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input wire in_ready,
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output wire out_ready
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);
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assign out_ready = 1'b1;
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reg [DATA_WIDTH - 1:0] regx_in_data[WINDOWS_WIDTH-1];
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wire [DATA_WIDTH - 1:0] regx_out_data[WINDOWS_WIDTH-1];
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reg [7:0] regx_in_user[WINDOWS_WIDTH-1];
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wire [7:0] regx_out_user[WINDOWS_WIDTH-1];
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reg [WINDOWS_WIDTH - 2:0] regx_in_valid;
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wire [WINDOWS_WIDTH - 2:0] regx_out_valid;
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reg [DATA_WIDTH - 1:0] data_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)];
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reg [7:0] user_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)];
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reg [7:0] out_user_windows[WINDOWS_WIDTH*WINDOWS_WIDTH];
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assign out_user = out_user_windows[(WINDOWS_WIDTH*WINDOWS_ANCHOR_Y) + WINDOWS_ANCHOR_X];
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/* outdata[x]:
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SHIFT_REG1 -> 0 3 6 . .
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SHIFT_REG0 -> 1 4 7 . .
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in_data -> 2 5 8 . .
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. . .
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. . .
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*/
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reg out_valid_output;
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reg firstframedone;
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always @(posedge clk) begin
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if(reset) firstframedone <= 0;
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else if(out_user == 1'b1) firstframedone <= 1;
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else firstframedone <= firstframedone;
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end
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always @(posedge clk) begin
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if(reset) out_valid_output <= 0;
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else out_valid_output <= regx_out_valid[WINDOWS_WIDTH-2];
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end
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assign out_valid = out_valid_output & (firstframedone || out_user);
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integer i,j;
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always @(posedge clk) begin
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if(reset)begin
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for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH;i=i+1) out_data[i] <= 0;
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for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH;i=i+1) out_user_windows[i] <= 0;
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end else if(regx_out_valid[WINDOWS_WIDTH-2])begin
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for(i=0;i<WINDOWS_WIDTH;i=i+1) begin
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for(j=0;j<WINDOWS_WIDTH;j=j+1) begin
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if(i==WINDOWS_WIDTH-1) begin
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if(j==0) out_data[(WINDOWS_WIDTH*i)+j] <= regx_out_data[WINDOWS_WIDTH-2];
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else out_data[(WINDOWS_WIDTH*i)+j] <= data_out_shift[j-1][2*j-1];
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end
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else out_data[(WINDOWS_WIDTH*i)+j] <= out_data[(WINDOWS_WIDTH*(i+1))+j];
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end
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end
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for(i=0;i<WINDOWS_WIDTH;i=i+1) begin
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for(j=0;j<WINDOWS_WIDTH;j=j+1) begin
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if(i==WINDOWS_WIDTH-1) begin
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if(j==0) out_user_windows[(WINDOWS_WIDTH*i)+j] <= regx_out_user[WINDOWS_WIDTH-2];
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else out_user_windows[(WINDOWS_WIDTH*i)+j] <= user_out_shift[j-1][2*j-1];
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end
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else out_user_windows[(WINDOWS_WIDTH*i)+j] <= out_user_windows[(WINDOWS_WIDTH*(i+1))+j];
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end
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end
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end else begin
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for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH-1;i=i+1) out_data[i] <= out_data[i];
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for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH-1;i=i+1) out_user_windows[i] <= out_user_windows[i];
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end
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end
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always @(posedge clk) begin
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if(reset) for(i=0;i<WINDOWS_WIDTH-1;i=i+1) for(j=0;j<WINDOWS_WIDTH-1;j=j+1) begin
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data_out_shift[i][j] <= 0;
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user_out_shift[i][j] <= 0;
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end else for(i=0;i<WINDOWS_WIDTH-1;i=i+1) begin
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for(j=0;j<2*(WINDOWS_WIDTH-1);j=j+1) begin
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if(i==WINDOWS_WIDTH-2 && j==0) data_out_shift[i][j] <= in_data;
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else if(j==0) data_out_shift[i][j] <= regx_out_data[(WINDOWS_WIDTH-2-i)-1];
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else data_out_shift[i][j] <= data_out_shift[i][j-1];
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if(i==WINDOWS_WIDTH-2 && j==0) user_out_shift[i][j] <= in_user;
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else if(j==0) user_out_shift[i][j] <= regx_out_user[(WINDOWS_WIDTH-2-i)-1];
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else user_out_shift[i][j] <= user_out_shift[i][j-1];
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end
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end
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end
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always @(*) begin
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for(i=0;i<WINDOWS_WIDTH-1;i=i+1)begin
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if(i == 0) regx_in_data[i] = in_data;
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else regx_in_data[i] = regx_out_data[i-1];
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end
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for(i=0;i<WINDOWS_WIDTH-1;i=i+1)begin
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if(i == 0) regx_in_user[i] = in_user;
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else regx_in_user[i] = regx_out_user[i-1];
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end
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for(i=0;i<WINDOWS_WIDTH-1;i=i+1)begin
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if(i == 0) regx_in_valid[i] = in_valid;
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else regx_in_valid[i] = regx_out_valid[i-1];
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end
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end
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generate
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genvar o;
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for(o = 0; o < WINDOWS_WIDTH - 1; o = o + 1'b1) begin:shift_register
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SHIFT_REGISTER #(
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.DATA_WIDTH(DATA_WIDTH),
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.IFOUTIMME(1'b1)
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)shift_registerx(
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.clk (clk),
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.reset (reset),
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.in_data (regx_in_data[o]),
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.in_user (regx_in_user[o]),
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.out_data (regx_out_data[o]),
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.out_user (regx_out_user[o]),
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.in_valid (regx_in_valid[o]),
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.out_valid(regx_out_valid[o])
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);
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end
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endgenerate
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endmodule |