SikongJueluo e29dce1d7e change isp output port and crop ip

2024-05-14 21:25:59 +08:00

Crop

change isp output port and crop ip

2024-05-14 21:25:59 +08:00

Demosaic

finish domosaic2 simulate

2024-05-14 21:00:19 +08:00

FIFO

first commit

2024-05-09 22:36:04 +08:00

Merge

fix some bugs

2024-05-13 16:52:13 +08:00

RAM

fix some bugs

2024-05-13 16:52:13 +08:00

Scaler

update scaler and RAM

2024-05-11 21:53:35 +08:00

sim

change isp output port and crop ip

2024-05-14 21:25:59 +08:00

.gitignore

finish domosaic2 simulate

2024-05-14 21:00:19 +08:00

isp.v

change isp output port and crop ip

2024-05-14 21:25:59 +08:00

Description

No description provided

9.6 MiB

Languages

Verilog 60.1%

C++ 25.7%

SystemVerilog 8.8%

Coq 4.8%

CMake 0.4%

Other 0.1%