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change isp output port and crop ip

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SikongJueluo
2024-05-14 21:25:59 +08:00
parent 507f116560
commit e29dce1d7e
5 changed files with 75 additions and 106 deletions
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96
Crop/crop.v
View File

@@ -15,69 +15,77 @@ module crop #(
input [3 * COLOR_DEPTH - 1:0] data_in,
output out_en,
input out_que,
output reg [3 * COLOR_DEPTH - 1:0] data_out
);
wire fifo_full, fifo_empty;
localparam READ_DATA = 0;
localparam HANDLE_DATA = 1;
localparam SEND_DATA = 2;
reg [1:0] state, nextState;
reg [11:0] cnt_x, cnt_y;
reg fifo_en;
reg [3 * COLOR_DEPTH - 1:0] data;
async_fifo #(
.DSIZE(3 * COLOR_DEPTH),
.ASIZE(128)
) fifo_image (
.wclk(clk),
.wrst_n(reset),
.rclk(clk),
.rrst_n(reset),
// 状态切换
always @(posedge clk or posedge reset) begin
if (reset)
state <= READ_DATA;
else
state <= nextState;
end
.winc(fifo_en),
.wdata(data_in),
.wfull(fifo_full),
.awfull(),
.rinc(out_en),
.rdata(data_out),
.rempty(fifo_empty),
.arempty()
);
assign in_que = !fifo_full;
assign out_en = (out_que && !fifo_empty) ? 1 : 0;
// 下一状态更新
always @(*) begin
case (state)
READ_DATA: nextState <= (in_que && in_en) ? HANDLE_DATA : READ_DATA;
HANDLE_DATA: nextState <= SEND_DATA;
SEND_DATA: nextState <= READ_DATA;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_en <= 0;
cnt_x <= 0;
cnt_y <= 0;
data <= 0;
end
else begin
if (in_en) begin
if (OFFSET_Y <= cnt_y && cnt_y < (OFFSET_Y + OUT_HEIGHT)) begin
if (OFFSET_X <= cnt_x && cnt_x < (OFFSET_X + OUT_WIDTH)) begin
fifo_en <= 1;
end
else begin
fifo_en <= 0;
case (state)
READ_DATA: begin
in_que <= 1;
if (in_en) begin
data <= data_in;
in_que <= 0;
end
end
else begin
fifo_en <= 0;
end
cnt_x <= cnt_x + 1;
if (cnt_x >= (OFFSET_X + OUT_WIDTH)) begin
cnt_x <= 0;
if (cnt_y >= (OFFSET_Y + OUT_HEIGHT)) begin
cnt_y <= 0;
HANDLE_DATA: begin
if (OFFSET_Y <= cnt_y && cnt_y < (OFFSET_Y + OUT_HEIGHT)) begin
if (OFFSET_X <= cnt_x && cnt_x < (OFFSET_X + OUT_WIDTH)) begin
out_en <= 1;
end
end
if (cnt_x >= (OFFSET_X + OUT_WIDTH)) begin
cnt_x <= 0;
if (cnt_y >= (OFFSET_Y + OUT_HEIGHT)) begin
cnt_y <= 0;
end
else begin
cnt_y <= cnt_y + 1;
end
end
else begin
cnt_y <= cnt_y + 1;
cnt_x <= cnt_x + 1;
end
end
end
SEND_DATA: begin
data_out <= data;
out_en <= 0;
end
endcase
end
end

16
isp.v
View File

@@ -16,7 +16,6 @@ module isp #(
input data_en,
input [15:0] data_in [2:0], // 数据输入线，0、1、2分别表示第一、二、三行
output reg data_que, // 数据请求线，高电平：请求三个数据，直到读取完才拉低
output reg data_line, // 新一行请求数据线，高电平：请求九个数据，直到读取完才拉低
output out_clk,
output out_en,
@@ -32,9 +31,9 @@ module isp #(
reg [3 * COLOR_DEPTH - 1:0] scale_in_data;
// 写入RAM
wire RAM_in_en;
wire RAM_in_que; // RAM 请求数据
wire [3 * COLOR_DEPTH - 1:0] RAM_in_data;
// wire RAM_in_en;
// wire RAM_in_que; // RAM 请求数据
// wire [3 * COLOR_DEPTH - 1:0] RAM_in_data;
assign out_clk = clk;
@@ -47,7 +46,6 @@ module isp #(
.data_en(data_en),
.data_in(data_in),
.data_que(data_que),
.data_line(data_line),
.out_en(rgb_en),
.out_r(im_red),
.out_g(im_green),
@@ -59,9 +57,6 @@ module isp #(
.reset(reset),
.in_en(rgb_en),
.data_in({im_red[11:0], im_green[11:0], im_red[11:0]}),
// .data_in[0](im_red[11:0]),
// .data_in[1](im_green[11:0]),
// .data_in[2](im_red[11:0]),
.data_que(scale_in_que),
.out_en(scale_in_en),
@@ -76,9 +71,8 @@ module isp #(
.in_que(scale_in_que),
.data_in(scale_in_data),
.out_en(RAM_in_en),
.out_que(RAM_in_que),
.data_out(RAM_in_data)
.out_en(out_en),
.data_out(data_out)
);
// RGB_to_RAM write_to_RAM (

4
Makefile → sim/Makefile
View File

@@ -54,7 +54,7 @@ VERILATOR_FLAGS += --assert
TOP_MODULE = isp
VERILATOR_FLAGS += -top $(TOP_MODULE)
# Input files for Verilator
VERILATOR_INPUT = isp.v sc_main.cpp ./Demosaic/demosaic2.v ./Crop/*.v ./FIFO/*.v ./Merge/*.v ./RAM/*.v
VERILATOR_INPUT = ../isp.v sc_main.cpp ../Demosaic/demosaic2.v ../Crop/*.v ../FIFO/*.v ../Merge/*.v ../RAM/*.v
# Check if SC exists via a verilator call (empty if not)
SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)
@@ -88,7 +88,7 @@ run:
@echo "-- RUN ---------------------"
@rm -rf logs
@mkdir -p logs
obj_dir/Vtop +trace
obj_dir/V$(TOP_MODULE) +trace
@echo
@echo "-- COVERAGE ----------------"

32
sc_main.cpp → sim/sc_main.cpp
View File

@@ -10,7 +10,7 @@
#include <sys/stat.h> // mkdir
// Include model header, generated from Verilating "top.v"
// Include model header, generated from Verilating "isp.v"
#include "Visp.h"
using namespace sc_core;
@@ -53,20 +53,20 @@ int sc_main(int argc, char* argv[]) {
sc_signal<uint64_t> out_quad;
sc_signal<sc_bv<70>> out_wide;
// Construct the Verilated model, from inside Vtop.h
// Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end
const std::unique_ptr<Vtop> top{new Vtop{"top"}};
// Construct the Verilated model, from inside Visp.h
// Using unique_ptr is similar to "Visp* isp = new Visp" then deleting at end
const std::unique_ptr<Visp> isp{new Visp{"isp"}};
// Attach Vtop's signals to this upper model
top->clk(clk);
top->fastclk(fastclk);
top->reset_l(reset_l);
top->in_small(in_small);
top->in_quad(in_quad);
top->in_wide(in_wide);
top->out_small(out_small);
top->out_quad(out_quad);
top->out_wide(out_wide);
// Attach Visp's signals to this upper model
isp->clk(clk);
isp->fastclk(fastclk);
isp->reset_l(reset_l);
isp->in_small(in_small);
isp->in_quad(in_quad);
isp->in_wide(in_wide);
isp->out_small(out_small);
isp->out_quad(out_quad);
isp->out_wide(out_wide);
// You must do one evaluation before enabling waves, in order to allow
// SystemC to interconnect everything for testing.
@@ -79,7 +79,7 @@ int sc_main(int argc, char* argv[]) {
if (flag && 0 == std::strcmp(flag, "+trace")) {
std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
tfp = new VerilatedVcdSc;
top->trace(tfp, 99); // Trace 99 levels of hierarchy
isp->trace(tfp, 99); // Trace 99 levels of hierarchy
Verilated::mkdir("logs");
tfp->open("logs/vlt_dump.vcd");
}
@@ -102,7 +102,7 @@ int sc_main(int argc, char* argv[]) {
}
// Final model cleanup
top->final();
isp->final();
// Close trace if opened
if (tfp) {

33
sim/tb_isp.v
View File

@@ -1,33 +0,0 @@
`include "isp.v"
`default_nettype none
module tb_isp;
reg clk;
reg rst_n;
isp
(
.rst_n (rst_n),
.clk (clk),
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD/2) clk=~clk;
// initial begin
// $dumpfile("tb_isp.vcd");
// $dumpvars(0, tb_isp);
// end
initial begin
#1 rst_n<=1'bx;clk<=1'bx;
#(CLK_PERIOD*3) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;
$finish(2);
end
endmodule
`default_nettype wire