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finish domosaic2 simulate

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SikongJueluo 2024-05-14 21:00:19 +08:00
parent ee812630dd
commit 507f116560
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11 changed files with 88 additions and 524348 deletions
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8
.gitignore vendored
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@ -4,4 +4,10 @@
*.wlf
*.mpf
*.mti
**/obj_dir/
**/obj_dir/
**/logs/
*.vcd
*.tif
*.bin
*.dat
*.png

54
Demosaic/demosaic2.v
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@ -12,7 +12,6 @@ module demosaic2 #(
input data_en,
input [DATA_SIZE - 1:0] data_in [2:0], // 数据输入线，0、1、2分别表示第一、二、三行
output reg data_que, // 数据请求线，高电平：请求三个数据，直到读取完才拉低
output reg data_line, // 新一行请求数据线，高电平：请求九个数据，直到读取完才拉低
// en: 输出数据有效信号，高电平有效
output reg out_en,
@ -46,7 +45,7 @@ module demosaic2 #(
end
// 下一状态更新
always @(*) begin
always @(state or cnt_data) begin
case (state)
// 记录够3x3个数据后，进行rgb转换
READ_DATA: nextState = (cnt_data >= 3) ? COLOR_GEN : READ_DATA;
@ -65,7 +64,6 @@ module demosaic2 #(
out_g <= 0;
out_r <= 0;
data_que <= 0;
data_line <= 1;
// 内部寄存器初始化
pos_x <= 0;
@ -78,28 +76,32 @@ module demosaic2 #(
case (state)
// 读取数据
READ_DATA: begin
data_que <= 1;
if (cnt_data < 2)
data_line <= 1;
// 请求数据
if (cnt_data <= 2) begin
data_que <= 1;
end
if (data_en) begin
data_cache[cnt_data][0] <= data_in[0];
data_cache[cnt_data][1] <= data_in[1];
data_cache[cnt_data][2] <= data_in[2];
cnt_data <= cnt_data + 1;
data_que <= 0;
end
end
COLOR_GEN: begin
// 取消数据请求
data_que <= 0;
data_line <= 0;
// 生成rgb图像
// data case 0 case 1 case 2 case 3
// 0 1 2 G R G R G R B G B G B G
// 3 4 5 B G B G B G G R G R G R
// 6 7 8 G R G R G R B G B G B G
case (raw_type)
0: begin // Missing B, R on G
red <= (data_cache[0][1] + data_cache[2][1]) / 2;
blue <= (data_cache[1][0] + data_cache[1][2]) / 2;
blue <= (data_cache[0][1] + data_cache[2][1]) / 2;
red <= (data_cache[1][0] + data_cache[1][2]) / 2;
green <= data_cache[1][1];
end
@ -116,12 +118,18 @@ module demosaic2 #(
end
3: begin // Missing B, R on G
blue <= (data_cache[0][1] + data_cache[2][1]) / 2;
red <= (data_cache[1][0] + data_cache[1][2]) / 2;
red <= (data_cache[0][1] + data_cache[2][1]) / 2;
blue <= (data_cache[1][0] + data_cache[1][2]) / 2;
green <= data_cache[1][1];
end
endcase
raw_type <= raw_type + 1;
case (raw_type)
0: raw_type <= 1;
1: raw_type <= 0;
2: raw_type <= 3;
3: raw_type <= 2;
endcase
end
WRITE_DATA: begin
@ -138,23 +146,23 @@ module demosaic2 #(
// 记录位置寄存器自增，并处理缓存数据
pos_x <= pos_x + 1;
if (pos_x >= IM_WIDTH - 2) begin
if (pos_x >= IM_WIDTH - 2 - 1) begin
cnt_data <= 0;
pos_x <= 0;
pos_y <= pos_y + 1;
if (pos_y >= IM_HEIGHT - 2)
if (pos_y >= IM_HEIGHT - 2 - 1)
pos_y <= 0;
end
else begin
cnt_data <= 2;
// 窗口右移
data_cache[0][0] <= data_cache[0][1];
data_cache[1][0] <= data_cache[1][1];
data_cache[2][0] <= data_cache[2][1];
data_cache[0][1] <= data_cache[0][2];
data_cache[1][1] <= data_cache[1][2];
data_cache[2][1] <= data_cache[2][2];
data_cache[0][0] <= data_cache[1][0];
data_cache[0][1] <= data_cache[1][1];
data_cache[0][2] <= data_cache[1][2];
data_cache[1][0] <= data_cache[2][0];
data_cache[1][1] <= data_cache[2][1];
data_cache[1][2] <= data_cache[2][2];
end
end
endcase

5
Demosaic/sim/Makefile
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@ -91,11 +91,6 @@ run:
@mkdir -p logs
obj_dir/V$(TOP_MODULE) +trace
@echo
@echo "-- COVERAGE ----------------"
@rm -rf logs/annotated
$(VERILATOR_COVERAGE) --annotate logs/annotated logs/coverage.dat
@echo
@echo "-- DONE --------------------"
@echo "To see waveforms, open vlt_dump.vcd in a waveform viewer"

35
Demosaic/sim/sc_demosaic.cpp
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@ -39,7 +39,9 @@ int sc_main(int argc, char* argv[]) {
// Read image
uint8_t buf[IM_SIZE * 2] = {0};
in_image.read((char*)buf, IM_SIZE);
in_image.read((char*)buf, IM_SIZE * 2);
// for (uint32_t i = 0; i < IM_SIZE * 2; i++)
// printf("0x%02x\t", buf[i]);
in_image.close();
// Reshape data
uint16_t image[IM_HEIGHT][IM_WIDTH] = {0};
@ -47,6 +49,7 @@ int sc_main(int argc, char* argv[]) {
for (int y = 0; y < IM_HEIGHT; y++) {
for (int x = 0; x < IM_WIDTH; x++) {
image[y][x] = (uint16_t)buf[i] + ((uint16_t)buf[i + 1] << 8);
i++;
}
}
@ -83,7 +86,6 @@ int sc_main(int argc, char* argv[]) {
sc_signal<bool> in_en;
sc_signal<bool> in_que;
sc_signal<bool> in_line;
sc_signal<uint32_t> data_in[3];
sc_signal<bool> out_en;
@ -99,7 +101,6 @@ int sc_main(int argc, char* argv[]) {
demo->reset(reset);
demo->data_en(in_en);
demo->data_que(in_que);
demo->data_line(in_line);
demo->data_in[0](data_in[0]);
demo->data_in[1](data_in[1]);
demo->data_in[2](data_in[2]);
@ -125,8 +126,11 @@ int sc_main(int argc, char* argv[]) {
}
// Simulate until $finish
bool flag_posedge = 0;
bool clk_last = 0, clk_now = 0;
uint16_t pos_x = 0, pos_y = 0;
uint32_t out[IM_SIZE] = {0}, out_head = 0;
uint16_t out[IM_SIZE] = {0};
uint32_t out_head = 0;
while (!Verilated::gotFinish()) {
// Flush the wave files each cycle so we can immediately see the output
// Don't do this in "real" programs, do it in an abort() handler instead
@ -139,11 +143,23 @@ int sc_main(int argc, char* argv[]) {
reset.write(0); // Deassert reset
}
// Clock posedge generatre
clk_now = clk.read();
if (!clk_last && clk_now)
flag_posedge = 1;
clk_last = clk_now;
// Send image data and Read RGB image data
if (sc_time_stamp() > sc_time(10, SC_NS) && clk.posedge()) {
if (sc_time_stamp() > sc_time(10, SC_NS) && flag_posedge) {
flag_posedge = 0;
// Send image data to demosaic
if (in_que.read() && pos_y < IM_HEIGHT) {
if (in_que.read() && pos_y < IM_HEIGHT - 2) {
in_en.write(1);
printf("x=%3d, y=%3d, data=0x%04x\t", pos_x, pos_y, image[pos_y + 0][pos_x]);
printf("x=%3d, y=%3d, data=0x%04x\t", pos_x, pos_y, image[pos_y + 1][pos_x]);
printf("x=%3d, y=%3d, data=0x%04x\n", pos_x, pos_y, image[pos_y + 2][pos_x]);
data_in[0].write(image[pos_y + 0][pos_x++]);
data_in[1].write(image[pos_y + 1][pos_x++]);
data_in[2].write(image[pos_y + 2][pos_x++]);
@ -164,6 +180,8 @@ int sc_main(int argc, char* argv[]) {
}
}
if (sc_time_stamp() > sc_time(2600, SC_US))
break;
// Simulate 1ns
sc_start(1, SC_NS);
}
@ -177,11 +195,6 @@ int sc_main(int argc, char* argv[]) {
tfp = nullptr;
}
// Coverage analysis (calling write only after the test is known to pass)
#if VM_COVERAGE
Verilated::mkdir("logs");
VerilatedCov::write("logs/coverage.dat");
#endif
// Save final output image
for (uint32_t i = 0; i < IM_SIZE; i++) {
buf[i * 2] = (out[i] & 0xffff0000) >> 16;

262144
Demosaic/sim/test.dat
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0
Demosaic/sim/test.raw
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12
Demosaic/sim/transform/raw_cut.py
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@ -5,15 +5,19 @@ cut_width = 512
cut_height = 256
if __name__ == '__main__':
txt = open('./test.dat', 'w')
# txt = open('./test.dat', 'w')
binfile = open('./test.bin', "wb")
image = imageio.imread_v2('./im.tif')
print(image.shape)
cut = image[0:cut_height, 0:cut_width]
print(cut.shape)
cut = np.array(cut, dtype=np.int16)
for data in list(cut.flatten()):
txt.write('%02x\n%02x\n' % (data & 0x00ff, (data & 0xff00) >> 4))
txt.close()
# txt.write('%02x\n%02x\n' % (data & 0x00ff, (data & 0xff00) >> 4))
binfile.write(data)
# txt.close()
binfile.close()
imageio.imsave('./test.tif', cut)
# imageio.imsave('./test.tif', cut)

8
Demosaic/sim/transform/raw_to_image.py
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@ -1,10 +1,10 @@
import imageio
import numpy as np
im_width = 1936
im_height = 1088
im_width = 512
im_height = 256
if __name__ == '__main__':
raw = np.fromfile('./test.raw', dtype=np.int8)
raw = np.fromfile('./out.bin', dtype=np.int16)
image = raw.reshape((im_height, im_width))
imageio.imsave("./test.tif", image)
imageio.imsave("./out.png", image)

262144
Demosaic/sim/transform/test.dat
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BIN
Demosaic/sim/transform/test.tif
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26
isp.v
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@ -18,9 +18,9 @@ module isp #(
output reg data_que, // 数据请求线，高电平：请求三个数据，直到读取完才拉低
output reg data_line, // 新一行请求数据线，高电平：请求九个数据，直到读取完才拉低
input out_que,
output out_clk,
output out_en,
output [15:0] data_out
output [31:0] data_out
);
// 三通道合成RGB图像
wire rgb_en;
@ -36,6 +36,8 @@ module isp #(
wire RAM_in_que; // RAM 请求数据
wire [3 * COLOR_DEPTH - 1:0] RAM_in_data;
assign out_clk = clk;
demosaic2 #(
.IM_WIDTH(1936),
.IM_HEIGHT(1088),
@ -79,17 +81,17 @@ module isp #(
.data_out(RAM_in_data)
);
RGB_to_RAM write_to_RAM (
.clk(clk),
.reset(reset),
// RGB_to_RAM write_to_RAM (
// .clk(clk),
// .reset(reset),
.in_en(RAM_in_en),
.in_que(RAM_in_que),
.data_in(RAM_in_data),
// .in_en(RAM_in_en),
// .in_que(RAM_in_que),
// .data_in(RAM_in_data),
.write_que(out_que),
.write_en(out_en),
.data_write(data_out)
);
// .write_que(out_que),
// .write_en(out_en),
// .data_write(data_out)
// );
endmodule