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ISP
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Verilog 60.1%
C++ 25.7%
SystemVerilog 8.8%
Coq 4.8%
CMake 0.4%
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SikongJueluo 507f116560
finish domosaic2 simulate 		2024-05-14 21:00:19 +08:00
Crop fix some bugs 2024-05-13 16:52:13 +08:00
Demosaic finish domosaic2 simulate 2024-05-14 21:00:19 +08:00
FIFO first commit 2024-05-09 22:36:04 +08:00
Merge fix some bugs 2024-05-13 16:52:13 +08:00
RAM fix some bugs 2024-05-13 16:52:13 +08:00
Scaler update scaler and RAM 2024-05-11 21:53:35 +08:00
sim first commit 2024-05-09 22:36:04 +08:00
.gitignore finish domosaic2 simulate 2024-05-14 21:00:19 +08:00
Makefile fix some bugs and pass lint check 2024-05-13 11:29:03 +08:00
isp.v finish domosaic2 simulate 2024-05-14 21:00:19 +08:00
sc_main.cpp fix some bugs and pass lint check 2024-05-13 11:29:03 +08:00