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Verilog 60.1%
C++ 25.7%
SystemVerilog 8.8%
Coq 4.8%
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SikongJueluo f3f01c1c51
update image processor to merge 3 chanels color into a RGB image 		2024-05-11 17:43:26 +08:00
CFA fix some warning 2024-05-10 21:41:47 +08:00
FIFO first commit 2024-05-09 22:36:04 +08:00
IM_PROCESS update image processor to merge 3 chanels color into a RGB image 2024-05-11 17:43:26 +08:00
RAM update image processor to merge 3 chanels color into a RGB image 2024-05-11 17:43:26 +08:00
sim first commit 2024-05-09 22:36:04 +08:00
.gitignore fix some warning 2024-05-10 21:41:47 +08:00
Makefile fix some warning 2024-05-10 21:41:47 +08:00
isp.v update image processor to merge 3 chanels color into a RGB image 2024-05-11 17:43:26 +08:00
sc_main.cpp fix some warning 2024-05-10 21:41:47 +08:00