fix some warning

This commit is contained in:
SikongJueluo 2024-05-10 21:41:47 +08:00
parent 7c9d5d7696
commit 9fc9627fc8
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GPG Key ID: D2D3D29A993716EA
5 changed files with 262 additions and 13 deletions

4
.gitignore vendored
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@ -1,5 +1,7 @@
.idea/
.vscode/
/CFA/sim/work/**
*.wlf
*.mpf
*.mti
*.mti
/obj_dir/

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@ -21,7 +21,7 @@ module demosaic2 #(
);
// 常量包括状态机
localparam IM_SIZE = IM_HEIGHT * IM_WIDTH;
// localparam IM_SIZE = IM_HEIGHT * IM_WIDTH;
localparam READ_DATA = 0;
localparam COLOR_GEN = 1;
localparam WRITE_DATA = 2;
@ -141,19 +141,19 @@ module demosaic2 #(
cnt_data <= 0;
pos_x <= 0;
pos_y <= pos_y + 1;
// if (pos_y >= IM_HEIGHT - 2)
// pos_y <= 0;
if (pos_y >= IM_HEIGHT - 2)
pos_y <= 0;
end
else begin
cnt_data <= 2;
// 窗口右移
data_cache[0][0] = data_cache[0][1];
data_cache[1][0] = data_cache[1][1];
data_cache[2][0] = data_cache[2][1];
data_cache[0][1] = data_cache[0][2];
data_cache[1][1] = data_cache[1][2];
data_cache[2][1] = data_cache[2][2];
data_cache[0][0] <= data_cache[0][1];
data_cache[1][0] <= data_cache[1][1];
data_cache[2][0] <= data_cache[2][1];
data_cache[0][1] <= data_cache[0][2];
data_cache[1][1] <= data_cache[1][2];
data_cache[2][1] <= data_cache[2][2];
end
end
endcase

116
Makefile Normal file
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@ -0,0 +1,116 @@
######################################################################
#
# DESCRIPTION: Verilator Example: Small Makefile
#
# This calls the object directory makefile. That allows the objects to
# be placed in the "current directory" which simplifies the Makefile.
#
# This file ONLY is placed under the Creative Commons Public Domain, for
# any use, without warranty, 2020 by Wilson Snyder.
# SPDX-License-Identifier: CC0-1.0
#
######################################################################
# Check for sanity to avoid later confusion
ifneq ($(words $(CURDIR)),1)
$(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)')
endif
######################################################################
# Set up variables
# If $VERILATOR_ROOT isn't in the environment, we assume it is part of a
# package install, and verilator is in your path. Otherwise find the
# binary relative to $VERILATOR_ROOT (such as when inside the git sources).
ifeq ($(VERILATOR_ROOT),)
VERILATOR = verilator
VERILATOR_COVERAGE = verilator_coverage
else
export VERILATOR_ROOT
VERILATOR = $(VERILATOR_ROOT)/bin/verilator
VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage
endif
VERILATOR_FLAGS =
# Generate SystemC in executable form
VERILATOR_FLAGS += -sc --exe
# Generate makefile dependencies (not shown as complicates the Makefile)
#VERILATOR_FLAGS += -MMD
# Optimize
# VERILATOR_FLAGS += -x-assign fast
# Warn abount lint issues; may not want this on less solid designs
VERILATOR_FLAGS += -Wall
# Make waveforms
VERILATOR_FLAGS += --trace
# Check SystemVerilog assertions
VERILATOR_FLAGS += --assert
# Generate coverage analysis
# VERILATOR_FLAGS += --coverage
# Run Verilator in debug mode
#VERILATOR_FLAGS += --debug
# Add this trace to get a backtrace in gdb
#VERILATOR_FLAGS += --gdbbt
# Input files for Verilator
VERILATOR_INPUT = -top isp isp.v sc_main.cpp ./CFA/demosaic2.v
# Check if SC exists via a verilator call (empty if not)
SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)
######################################################################
ifneq ($(SYSTEMC_EXISTS),)
default: run
else
default: nosc
endif
run:
@echo
@echo "-- Verilator tracing example"
@echo
@echo "-- VERILATE ----------------"
$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT)
@echo
@echo "-- COMPILE -----------------"
# To compile, we can either
# 1. Pass --build to Verilator by editing VERILATOR_FLAGS above.
# 2. Or, run the make rules Verilator does:
# $(MAKE) -j -C obj_dir -f Vtop.mk
# 3. Or, call a submakefile where we can override the rules ourselves:
$(MAKE) -j -C obj_dir -f ../Makefile_obj
@echo
@echo "-- RUN ---------------------"
@rm -rf logs
@mkdir -p logs
obj_dir/Vtop +trace
@echo
@echo "-- COVERAGE ----------------"
@rm -rf logs/annotated
$(VERILATOR_COVERAGE) --annotate logs/annotated logs/coverage.dat
@echo
@echo "-- DONE --------------------"
@echo "To see waveforms, open vlt_dump.vcd in a waveform viewer"
@echo
######################################################################
# Other targets
nosc:
@echo
@echo "%Skip: SYSTEMC_INCLUDE not in environment"
@echo "(If you have SystemC see the README, and rebuild Verilator)"
@echo
show-config:
$(VERILATOR) -V
maintainer-copy::
clean mostlyclean distclean maintainer-clean::
-rm -rf obj_dir logs *.log *.dmp *.vpd coverage.dat core

6
isp.v
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@ -3,8 +3,8 @@
module isp #(
parameter IN_WIDTH = 1936,
parameter IN_HEIGHT = 1088,
parameter OUT_WIDTH = 1936 - 2,
parameter OUT_HEIGHT = 1088 - 2,
// parameter OUT_WIDTH = 1936 - 2,
// parameter OUT_HEIGHT = 1088 - 2,
parameter RAW_TYPE = 3 // 0:grbg 1:rggb 2:bggr 3:gbrg
) (
// 基本信号
@ -37,4 +37,4 @@ module isp #(
.out_b(out_b)
);
endmodule
endmodule

131
sc_main.cpp Normal file
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@ -0,0 +1,131 @@
// For std::unique_ptr
#include <memory>
// SystemC global header
#include <systemc>
// Include common routines
#include <verilated.h>
#if VM_TRACE
#include <verilated_vcd_sc.h>
#endif
#include <sys/stat.h> // mkdir
// Include model header, generated from Verilating "top.v"
#include "Visp.h"
using namespace sc_core;
using namespace sc_dt;
int sc_main(int argc, char* argv[]) {
// This is a more complicated example, please also see the simpler examples/make_hello_c.
// Create logs/ directory in case we have traces to put under it
Verilated::mkdir("logs");
// Set debug level, 0 is off, 9 is highest presently used
// May be overridden by commandArgs argument parsing
Verilated::debug(0);
// Randomization reset policy
// May be overridden by commandArgs argument parsing
Verilated::randReset(2);
#if VM_TRACE
// Before any evaluation, need to know to calculate those signals only used for tracing
Verilated::traceEverOn(true);
#endif
// Pass arguments so Verilated code can see them, e.g. $value$plusargs
// This needs to be called before you create any model
Verilated::commandArgs(argc, argv);
// General logfile
std::ios::sync_with_stdio();
// Define clocks
sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
sc_clock fastclk{"fastclk", 2, SC_NS, 0.5, 2, SC_NS, true};
// Define interconnect
sc_signal<bool> reset_l;
sc_signal<uint32_t> in_small;
sc_signal<uint64_t> in_quad;
sc_signal<sc_bv<70>> in_wide;
sc_signal<uint32_t> out_small;
sc_signal<uint64_t> out_quad;
sc_signal<sc_bv<70>> out_wide;
// Construct the Verilated model, from inside Vtop.h
// Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end
const std::unique_ptr<Vtop> top{new Vtop{"top"}};
// Attach Vtop's signals to this upper model
top->clk(clk);
top->fastclk(fastclk);
top->reset_l(reset_l);
top->in_small(in_small);
top->in_quad(in_quad);
top->in_wide(in_wide);
top->out_small(out_small);
top->out_quad(out_quad);
top->out_wide(out_wide);
// You must do one evaluation before enabling waves, in order to allow
// SystemC to interconnect everything for testing.
sc_start(SC_ZERO_TIME);
#if VM_TRACE
// If verilator was invoked with --trace argument,
// and if at run time passed the +trace argument, turn on tracing
VerilatedVcdSc* tfp = nullptr;
const char* flag = Verilated::commandArgsPlusMatch("trace");
if (flag && 0 == std::strcmp(flag, "+trace")) {
std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
tfp = new VerilatedVcdSc;
top->trace(tfp, 99); // Trace 99 levels of hierarchy
Verilated::mkdir("logs");
tfp->open("logs/vlt_dump.vcd");
}
#endif
// Simulate until $finish
while (!Verilated::gotFinish()) {
#if VM_TRACE
// Flush the wave files each cycle so we can immediately see the output
// Don't do this in "real" programs, do it in an abort() handler instead
if (tfp) tfp->flush();
#endif
// Apply inputs
if (sc_time_stamp() > sc_time(1, SC_NS) && sc_time_stamp() < sc_time(10, SC_NS)) {
reset_l = !1; // Assert reset
} else {
reset_l = !0; // Deassert reset
}
// Simulate 1ns
sc_start(1, SC_NS);
}
// Final model cleanup
top->final();
// Close trace if opened
#if VM_TRACE
if (tfp) {
tfp->close();
tfp = nullptr;
}
#endif
// Coverage analysis (calling write only after the test is known to pass)
#if VM_COVERAGE
Verilated::mkdir("logs");
VerilatedCov::write("logs/coverage.dat");
#endif
// Return good completion status
return 0;
}