change isp output port and crop ip
This commit is contained in:
SikongJueluo
parent
507f116560
commit
e29dce1d7e
94
Crop/crop.v
94
Crop/crop.v
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@ -15,69 +15,77 @@ module crop #(
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input [3 * COLOR_DEPTH - 1:0] data_in,
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output out_en,
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input out_que,
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output reg [3 * COLOR_DEPTH - 1:0] data_out
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);
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wire fifo_full, fifo_empty;
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localparam READ_DATA = 0;
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localparam HANDLE_DATA = 1;
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localparam SEND_DATA = 2;
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reg [1:0] state, nextState;
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reg [11:0] cnt_x, cnt_y;
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reg fifo_en;
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reg [3 * COLOR_DEPTH - 1:0] data;
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async_fifo #(
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.DSIZE(3 * COLOR_DEPTH),
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.ASIZE(128)
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) fifo_image (
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.wclk(clk),
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.wrst_n(reset),
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.rclk(clk),
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.rrst_n(reset),
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// 状态切换
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always @(posedge clk or posedge reset) begin
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if (reset)
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state <= READ_DATA;
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else
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state <= nextState;
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end
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.winc(fifo_en),
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.wdata(data_in),
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.wfull(fifo_full),
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.awfull(),
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.rinc(out_en),
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.rdata(data_out),
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.rempty(fifo_empty),
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.arempty()
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);
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assign in_que = !fifo_full;
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assign out_en = (out_que && !fifo_empty) ? 1 : 0;
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// 下一状态更新
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always @(*) begin
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case (state)
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READ_DATA: nextState <= (in_que && in_en) ? HANDLE_DATA : READ_DATA;
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HANDLE_DATA: nextState <= SEND_DATA;
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SEND_DATA: nextState <= READ_DATA;
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endcase
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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fifo_en <= 0;
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cnt_x <= 0;
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cnt_y <= 0;
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data <= 0;
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end
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else begin
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if (in_en) begin
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case (state)
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READ_DATA: begin
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in_que <= 1;
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if (OFFSET_Y <= cnt_y && cnt_y < (OFFSET_Y + OUT_HEIGHT)) begin
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if (OFFSET_X <= cnt_x && cnt_x < (OFFSET_X + OUT_WIDTH)) begin
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fifo_en <= 1;
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if (in_en) begin
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data <= data_in;
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in_que <= 0;
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end
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else begin
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fifo_en <= 0;
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end
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end
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else begin
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fifo_en <= 0;
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end
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cnt_x <= cnt_x + 1;
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if (cnt_x >= (OFFSET_X + OUT_WIDTH)) begin
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cnt_x <= 0;
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if (cnt_y >= (OFFSET_Y + OUT_HEIGHT)) begin
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cnt_y <= 0;
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HANDLE_DATA: begin
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if (OFFSET_Y <= cnt_y && cnt_y < (OFFSET_Y + OUT_HEIGHT)) begin
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if (OFFSET_X <= cnt_x && cnt_x < (OFFSET_X + OUT_WIDTH)) begin
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out_en <= 1;
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end
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end
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if (cnt_x >= (OFFSET_X + OUT_WIDTH)) begin
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cnt_x <= 0;
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if (cnt_y >= (OFFSET_Y + OUT_HEIGHT)) begin
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cnt_y <= 0;
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end
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else begin
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cnt_y <= cnt_y + 1;
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end
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end
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else begin
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cnt_y <= cnt_y + 1;
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cnt_x <= cnt_x + 1;
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end
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end
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end
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SEND_DATA: begin
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data_out <= data;
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out_en <= 0;
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end
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endcase
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end
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end
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16
isp.v
16
isp.v
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@ -16,7 +16,6 @@ module isp #(
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input data_en,
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input [15:0] data_in [2:0], // 数据输入线，0、1、2分别表示第一、二、三行
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output reg data_que, // 数据请求线，高电平：请求三个数据，直到读取完才拉低
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output reg data_line, // 新一行请求数据线，高电平：请求九个数据，直到读取完才拉低
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output out_clk,
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output out_en,
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@ -32,9 +31,9 @@ module isp #(
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reg [3 * COLOR_DEPTH - 1:0] scale_in_data;
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// 写入RAM
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wire RAM_in_en;
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wire RAM_in_que; // RAM 请求数据
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wire [3 * COLOR_DEPTH - 1:0] RAM_in_data;
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// wire RAM_in_en;
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// wire RAM_in_que; // RAM 请求数据
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// wire [3 * COLOR_DEPTH - 1:0] RAM_in_data;
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assign out_clk = clk;
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@ -47,7 +46,6 @@ module isp #(
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.data_en(data_en),
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.data_in(data_in),
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.data_que(data_que),
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.data_line(data_line),
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.out_en(rgb_en),
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.out_r(im_red),
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.out_g(im_green),
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@ -59,9 +57,6 @@ module isp #(
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.reset(reset),
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.in_en(rgb_en),
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.data_in({im_red[11:0], im_green[11:0], im_red[11:0]}),
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// .data_in[0](im_red[11:0]),
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// .data_in[1](im_green[11:0]),
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// .data_in[2](im_red[11:0]),
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.data_que(scale_in_que),
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.out_en(scale_in_en),
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@ -76,9 +71,8 @@ module isp #(
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.in_que(scale_in_que),
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.data_in(scale_in_data),
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.out_en(RAM_in_en),
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.out_que(RAM_in_que),
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.data_out(RAM_in_data)
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.out_en(out_en),
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.data_out(data_out)
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);
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// RGB_to_RAM write_to_RAM (
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@ -54,7 +54,7 @@ VERILATOR_FLAGS += --assert
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TOP_MODULE = isp
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VERILATOR_FLAGS += -top $(TOP_MODULE)
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# Input files for Verilator
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VERILATOR_INPUT = isp.v sc_main.cpp ./Demosaic/demosaic2.v ./Crop/*.v ./FIFO/*.v ./Merge/*.v ./RAM/*.v
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VERILATOR_INPUT = ../isp.v sc_main.cpp ../Demosaic/demosaic2.v ../Crop/*.v ../FIFO/*.v ../Merge/*.v ../RAM/*.v
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# Check if SC exists via a verilator call (empty if not)
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SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)
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@ -88,7 +88,7 @@ run:
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@echo "-- RUN ---------------------"
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@rm -rf logs
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@mkdir -p logs
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obj_dir/Vtop +trace
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obj_dir/V$(TOP_MODULE) +trace
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@echo
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@echo "-- COVERAGE ----------------"
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@ -10,7 +10,7 @@
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#include <sys/stat.h> // mkdir
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// Include model header, generated from Verilating "top.v"
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// Include model header, generated from Verilating "isp.v"
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#include "Visp.h"
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using namespace sc_core;
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@ -53,20 +53,20 @@ int sc_main(int argc, char* argv[]) {
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sc_signal<uint64_t> out_quad;
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sc_signal<sc_bv<70>> out_wide;
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// Construct the Verilated model, from inside Vtop.h
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// Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end
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const std::unique_ptr<Vtop> top{new Vtop{"top"}};
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// Construct the Verilated model, from inside Visp.h
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// Using unique_ptr is similar to "Visp* isp = new Visp" then deleting at end
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const std::unique_ptr<Visp> isp{new Visp{"isp"}};
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// Attach Vtop's signals to this upper model
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top->clk(clk);
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top->fastclk(fastclk);
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top->reset_l(reset_l);
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top->in_small(in_small);
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top->in_quad(in_quad);
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top->in_wide(in_wide);
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top->out_small(out_small);
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top->out_quad(out_quad);
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top->out_wide(out_wide);
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// Attach Visp's signals to this upper model
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isp->clk(clk);
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isp->fastclk(fastclk);
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isp->reset_l(reset_l);
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isp->in_small(in_small);
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isp->in_quad(in_quad);
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isp->in_wide(in_wide);
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isp->out_small(out_small);
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isp->out_quad(out_quad);
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isp->out_wide(out_wide);
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// You must do one evaluation before enabling waves, in order to allow
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// SystemC to interconnect everything for testing.
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@ -79,7 +79,7 @@ int sc_main(int argc, char* argv[]) {
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if (flag && 0 == std::strcmp(flag, "+trace")) {
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std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
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tfp = new VerilatedVcdSc;
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top->trace(tfp, 99); // Trace 99 levels of hierarchy
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isp->trace(tfp, 99); // Trace 99 levels of hierarchy
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Verilated::mkdir("logs");
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tfp->open("logs/vlt_dump.vcd");
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}
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@ -102,7 +102,7 @@ int sc_main(int argc, char* argv[]) {
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}
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// Final model cleanup
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top->final();
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isp->final();
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// Close trace if opened
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if (tfp) {
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33
sim/tb_isp.v
33
sim/tb_isp.v
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@ -1,33 +0,0 @@
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`include "isp.v"
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`default_nettype none
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module tb_isp;
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reg clk;
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reg rst_n;
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isp
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(
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.rst_n (rst_n),
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.clk (clk),
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);
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localparam CLK_PERIOD = 10;
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always #(CLK_PERIOD/2) clk=~clk;
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// initial begin
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// $dumpfile("tb_isp.vcd");
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// $dumpvars(0, tb_isp);
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// end
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initial begin
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#1 rst_n<=1'bx;clk<=1'bx;
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#(CLK_PERIOD*3) rst_n<=1;
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#(CLK_PERIOD*3) rst_n<=0;clk<=0;
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$finish(2);
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end
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endmodule
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`default_nettype wire
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