change isp output port and crop ip

sim/Makefile

@@ -0,0 +1,118 @@
+######################################################################
+#
+# DESCRIPTION: Verilator Example: Small Makefile
+#
+# This calls the object directory makefile.  That allows the objects to
+# be placed in the "current directory" which simplifies the Makefile.
+#
+# This file ONLY is placed under the Creative Commons Public Domain, for
+# any use, without warranty, 2020 by Wilson Snyder.
+# SPDX-License-Identifier: CC0-1.0
+#
+######################################################################
+# Check for sanity to avoid later confusion
+
+ifneq ($(words $(CURDIR)),1)
+ $(error Unsupported: GNU Make cannot build in directories containing spaces, build elsewhere: '$(CURDIR)')
+endif
+
+######################################################################
+# Set up variables
+
+# If $VERILATOR_ROOT isn't in the environment, we assume it is part of a
+# package install, and verilator is in your path. Otherwise find the
+# binary relative to $VERILATOR_ROOT (such as when inside the git sources).
+ifeq ($(VERILATOR_ROOT),)
+VERILATOR = verilator
+VERILATOR_COVERAGE = verilator_coverage
+else
+export VERILATOR_ROOT
+VERILATOR = $(VERILATOR_ROOT)/bin/verilator
+VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage
+endif
+
+VERILATOR_FLAGS =
+# Generate SystemC in executable form
+VERILATOR_FLAGS += -sc --exe
+# Generate makefile dependencies (not shown as complicates the Makefile)
+#VERILATOR_FLAGS += -MMD
+# Optimize
+# VERILATOR_FLAGS += -x-assign fast
+# Warn abount lint issues; may not want this on less solid designs
+VERILATOR_FLAGS += -Wall
+# Make waveforms
+VERILATOR_FLAGS += --trace
+# Check SystemVerilog assertions
+VERILATOR_FLAGS += --assert
+# Generate coverage analysis
+# VERILATOR_FLAGS += --coverage
+# Run Verilator in debug mode
+#VERILATOR_FLAGS += --debug
+# Add this trace to get a backtrace in gdb
+#VERILATOR_FLAGS += --gdbbt
+# Specify top module
+TOP_MODULE = isp
+VERILATOR_FLAGS += -top $(TOP_MODULE)
+# Input files for Verilator
+VERILATOR_INPUT = ../isp.v sc_main.cpp ../Demosaic/demosaic2.v ../Crop/*.v ../FIFO/*.v ../Merge/*.v ../RAM/*.v
+
+# Check if SC exists via a verilator call (empty if not)
+SYSTEMC_EXISTS := $(shell $(VERILATOR) --get-supported SYSTEMC)
+
+######################################################################
+
+ifneq ($(SYSTEMC_EXISTS),)
+default: run
+else
+default: nosc
+endif
+
+run:
+	@echo
+	@echo "-- Verilator tracing example"
+
+	@echo
+	@echo "-- VERILATE ----------------"
+	$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_INPUT)
+
+	@echo
+	@echo "-- COMPILE -----------------"
+# To compile, we can either
+# 1. Pass --build to Verilator by editing VERILATOR_FLAGS above.
+# 2. Or, run the make rules Verilator does:
+#	$(MAKE) -j -C obj_dir -f Vtop.mk
+# 3. Or, call a submakefile where we can override the rules ourselves:
+	$(MAKE) -j -C obj_dir -f V$(TOP_MODULE).mk
+
+	@echo
+	@echo "-- RUN ---------------------"
+	@rm -rf logs
+	@mkdir -p logs
+	obj_dir/V$(TOP_MODULE) +trace
+
+	@echo
+	@echo "-- COVERAGE ----------------"
+	@rm -rf logs/annotated
+	$(VERILATOR_COVERAGE) --annotate logs/annotated logs/coverage.dat
+
+	@echo
+	@echo "-- DONE --------------------"
+	@echo "To see waveforms, open vlt_dump.vcd in a waveform viewer"
+	@echo
+
+
+######################################################################
+# Other targets
+
+nosc:
+	@echo
+	@echo "%Skip: SYSTEMC_INCLUDE not in environment"
+	@echo "(If you have SystemC see the README, and rebuild Verilator)"
+	@echo
+
+show-config:
+	$(VERILATOR) -V
+
+maintainer-copy::
+clean mostlyclean distclean maintainer-clean::
+	-rm -rf obj_dir logs *.log *.dmp *.vpd coverage.dat core

sim/sc_main.cpp

@@ -0,0 +1,121 @@
+// For std::unique_ptr
+#include <memory>
+
+// SystemC global header
+#include <systemc>
+
+// Include common routines
+#include <verilated.h>
+#include <verilated_vcd_sc.h>
+
+#include <sys/stat.h>  // mkdir
+
+// Include model header, generated from Verilating "isp.v"
+#include "Visp.h"
+
+using namespace sc_core;
+using namespace sc_dt;
+
+int sc_main(int argc, char* argv[]) {
+    // This is a more complicated example, please also see the simpler examples/make_hello_c.
+
+    // Create logs/ directory in case we have traces to put under it
+    Verilated::mkdir("logs");
+
+    // Set debug level, 0 is off, 9 is highest presently used
+    // May be overridden by commandArgs argument parsing
+    Verilated::debug(0);
+
+    // Randomization reset policy
+    // May be overridden by commandArgs argument parsing
+    Verilated::randReset(2);
+
+    // Before any evaluation, need to know to calculate those signals only used for tracing
+    Verilated::traceEverOn(true);
+
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    // This needs to be called before you create any model
+    Verilated::commandArgs(argc, argv);
+
+    // General logfile
+    std::ios::sync_with_stdio();
+
+    // Define clocks
+    sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true};
+    sc_clock fastclk{"fastclk", 2, SC_NS, 0.5, 2, SC_NS, true};
+
+    // Define interconnect
+    sc_signal<bool> reset_l;
+    sc_signal<uint32_t> in_small;
+    sc_signal<uint64_t> in_quad;
+    sc_signal<sc_bv<70>> in_wide;
+    sc_signal<uint32_t> out_small;
+    sc_signal<uint64_t> out_quad;
+    sc_signal<sc_bv<70>> out_wide;
+
+    // Construct the Verilated model, from inside Visp.h
+    // Using unique_ptr is similar to "Visp* isp = new Visp" then deleting at end
+    const std::unique_ptr<Visp> isp{new Visp{"isp"}};
+
+    // Attach Visp's signals to this upper model
+    isp->clk(clk);
+    isp->fastclk(fastclk);
+    isp->reset_l(reset_l);
+    isp->in_small(in_small);
+    isp->in_quad(in_quad);
+    isp->in_wide(in_wide);
+    isp->out_small(out_small);
+    isp->out_quad(out_quad);
+    isp->out_wide(out_wide);
+
+    // You must do one evaluation before enabling waves, in order to allow
+    // SystemC to interconnect everything for testing.
+    sc_start(SC_ZERO_TIME);
+
+    // If verilator was invoked with --trace argument,
+    // and if at run time passed the +trace argument, turn on tracing
+    VerilatedVcdSc* tfp = nullptr;
+    const char* flag = Verilated::commandArgsPlusMatch("trace");
+    if (flag && 0 == std::strcmp(flag, "+trace")) {
+        std::cout << "Enabling waves into logs/vlt_dump.vcd...\n";
+        tfp = new VerilatedVcdSc;
+        isp->trace(tfp, 99);  // Trace 99 levels of hierarchy
+        Verilated::mkdir("logs");
+        tfp->open("logs/vlt_dump.vcd");
+    }
+
+    // Simulate until $finish
+    while (!Verilated::gotFinish()) {
+        // Flush the wave files each cycle so we can immediately see the output
+        // Don't do this in "real" programs, do it in an abort() handler instead
+        if (tfp) tfp->flush();
+
+        // Apply inputs
+        if (sc_time_stamp() > sc_time(1, SC_NS) && sc_time_stamp() < sc_time(10, SC_NS)) {
+            reset_l = !1;  // Assert reset
+        } else {
+            reset_l = !0;  // Deassert reset
+        }
+
+        // Simulate 1ns
+        sc_start(1, SC_NS);
+    }
+
+    // Final model cleanup
+    isp->final();
+
+    // Close trace if opened
+    if (tfp) {
+        tfp->close();
+        tfp = nullptr;
+    }
+
+    // Coverage analysis (calling write only after the test is known to pass)
+#if VM_COVERAGE
+    Verilated::mkdir("logs");
+    VerilatedCov::write("logs/coverage.dat");
+#endif
+
+    // Return good completion status
+    return 0;
+}

sim/tb_isp.v

@@ -1,33 +0,0 @@
-`include "isp.v"
-`default_nettype none
-
-module tb_isp;
-reg clk;
-reg rst_n;
-
- isp
-(
-    .rst_n (rst_n),
-    .clk (clk),
-);
-
-localparam CLK_PERIOD = 10;
-always #(CLK_PERIOD/2) clk=~clk;
-
-// initial begin
-//     $dumpfile("tb_isp.vcd");
-//     $dumpvars(0, tb_isp);
-// end
-
-initial begin
-    #1 rst_n<=1'bx;clk<=1'bx;
-    #(CLK_PERIOD*3) rst_n<=1;
-    #(CLK_PERIOD*3) rst_n<=0;clk<=0;
-
-
-
-    $finish(2);
-end
-
-endmodule
-`default_nettype wire