change isp output port and crop ip

This commit is contained in:
SikongJueluo
2024-05-14 21:25:59 +08:00
parent 507f116560
commit e29dce1d7e
5 changed files with 75 additions and 106 deletions

View File

@@ -15,69 +15,77 @@ module crop #(
input [3 * COLOR_DEPTH - 1:0] data_in,
output out_en,
input out_que,
output reg [3 * COLOR_DEPTH - 1:0] data_out
);
wire fifo_full, fifo_empty;
localparam READ_DATA = 0;
localparam HANDLE_DATA = 1;
localparam SEND_DATA = 2;
reg [1:0] state, nextState;
reg [11:0] cnt_x, cnt_y;
reg fifo_en;
reg [3 * COLOR_DEPTH - 1:0] data;
async_fifo #(
.DSIZE(3 * COLOR_DEPTH),
.ASIZE(128)
) fifo_image (
.wclk(clk),
.wrst_n(reset),
.rclk(clk),
.rrst_n(reset),
// 状态切换
always @(posedge clk or posedge reset) begin
if (reset)
state <= READ_DATA;
else
state <= nextState;
end
.winc(fifo_en),
.wdata(data_in),
.wfull(fifo_full),
.awfull(),
.rinc(out_en),
.rdata(data_out),
.rempty(fifo_empty),
.arempty()
);
assign in_que = !fifo_full;
assign out_en = (out_que && !fifo_empty) ? 1 : 0;
// 下一状态更新
always @(*) begin
case (state)
READ_DATA: nextState <= (in_que && in_en) ? HANDLE_DATA : READ_DATA;
HANDLE_DATA: nextState <= SEND_DATA;
SEND_DATA: nextState <= READ_DATA;
endcase
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_en <= 0;
cnt_x <= 0;
cnt_y <= 0;
data <= 0;
end
else begin
if (in_en) begin
if (OFFSET_Y <= cnt_y && cnt_y < (OFFSET_Y + OUT_HEIGHT)) begin
if (OFFSET_X <= cnt_x && cnt_x < (OFFSET_X + OUT_WIDTH)) begin
fifo_en <= 1;
end
else begin
fifo_en <= 0;
case (state)
READ_DATA: begin
in_que <= 1;
if (in_en) begin
data <= data_in;
in_que <= 0;
end
end
else begin
fifo_en <= 0;
end
cnt_x <= cnt_x + 1;
if (cnt_x >= (OFFSET_X + OUT_WIDTH)) begin
cnt_x <= 0;
if (cnt_y >= (OFFSET_Y + OUT_HEIGHT)) begin
cnt_y <= 0;
HANDLE_DATA: begin
if (OFFSET_Y <= cnt_y && cnt_y < (OFFSET_Y + OUT_HEIGHT)) begin
if (OFFSET_X <= cnt_x && cnt_x < (OFFSET_X + OUT_WIDTH)) begin
out_en <= 1;
end
end
if (cnt_x >= (OFFSET_X + OUT_WIDTH)) begin
cnt_x <= 0;
if (cnt_y >= (OFFSET_Y + OUT_HEIGHT)) begin
cnt_y <= 0;
end
else begin
cnt_y <= cnt_y + 1;
end
end
else begin
cnt_y <= cnt_y + 1;
cnt_x <= cnt_x + 1;
end
end
end
SEND_DATA: begin
data_out <= data;
out_en <= 0;
end
endcase
end
end