reconstruct saturation and make it sync to clk
This commit is contained in:
parent
242f3527f8
commit
d9ab23defe
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@ -51,8 +51,8 @@ module ColorBlender #(
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endcase
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endcase
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end
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end
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assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
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assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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@ -38,8 +38,8 @@ module GammaCorrection2 #(
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endcase
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endcase
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end
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end
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assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
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assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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@ -62,7 +62,7 @@ module GammaCorrection2 #(
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end
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end
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SEND_DATA: begin
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SEND_DATA: begin
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if (in_ready) begin
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if (in_ready && !in_receive) begin
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out_en <= 1;
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out_en <= 1;
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if (enable) begin
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if (enable) begin
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out_data[0] <= gamma_table[data_cache[0]];
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out_data[0] <= gamma_table[data_cache[0]];
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@ -51,8 +51,8 @@ module GreyWorld #(
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endcase
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endcase
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end
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end
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assign out_ready = (!in_en && !reset) ? 1 : 0;
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assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign out_receive = (in_en && !reset) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign average = ((red_total + green_total + blue_total) << 8) / (3 * IM_SIZE);
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assign average = ((red_total + green_total + blue_total) << 8) / (3 * IM_SIZE);
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@ -19,13 +19,14 @@ module SaturationCorrection #(
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input wire enable,
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input wire enable,
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input wire signed [31:0] saturation_inc
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input wire signed [31:0] saturation_inc
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);
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);
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reg [2:0] state, nextState;
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reg [2:0] state, nextState, calState;
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localparam reg [2:0] READ_DATA = 0;
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localparam reg [2:0] READ_DATA = 0;
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localparam reg [2:0] CALC_DATA = 1;
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localparam reg [2:0] CALC_DATA = 1;
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localparam reg [2:0] SEND_DATA = 2;
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localparam reg [2:0] SEND_DATA = 2;
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reg signed [31:0] data_cal[3], data_cache[3];
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reg signed [31:0] data_cal[3], data_cache[3];
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wire signed [31:0] max, min, delta, value, light, saturation, alpha;
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// wire signed [31:0] max, min, delta, value, light, saturation, alpha;
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reg signed [31:0] max, min, delta, value, light, saturation, alpha;
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) state <= READ_DATA;
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if (reset) state <= READ_DATA;
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@ -34,39 +35,49 @@ module SaturationCorrection #(
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always @(*) begin
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always @(*) begin
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case (state)
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case (state)
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READ_DATA: nextState = in_en ? CALC_DATA : READ_DATA;
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READ_DATA: nextState = in_en ? 3 : READ_DATA;
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CALC_DATA: nextState = SEND_DATA;
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3: nextState = CALC_DATA;
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CALC_DATA: nextState = (calState >= 5 || !enable) ? SEND_DATA : CALC_DATA;
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SEND_DATA: nextState = in_receive ? READ_DATA : SEND_DATA;
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SEND_DATA: nextState = in_receive ? READ_DATA : SEND_DATA;
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default: nextState = READ_DATA;
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default: nextState = READ_DATA;
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endcase
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endcase
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end
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end
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assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
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assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign max = data_cache[0] > data_cache[1]?
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// assign max = data_cache[0] > data_cache[1]?
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(data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]):
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// (data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]):
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(data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]);
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// (data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]);
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assign min = data_cache[0] < data_cache[1]?
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// assign min = data_cache[0] < data_cache[1]?
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(data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]):
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// (data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]):
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(data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]);
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// (data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]);
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assign delta = max - min;
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// assign delta = max - min;
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assign value = max + min;
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// assign value = max + min;
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assign light = value >>> 1;
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// assign light = value >>> 1;
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// assign saturation = (light <= 128) ? (delta <<< 8) / value : (delta <<< 8) / (512 - value);
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// // // assign saturation = (light <= 128) ? (delta <<< 8) / value : (delta <<< 8) / (512 - value);
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assign saturation = (delta <<< 8) / max;
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// assign saturation = (delta <<< 8) / max;
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assign alpha = (saturation_inc[31] == 0)
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// assign alpha = (saturation_inc[31] == 0)
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? ((saturation_inc + saturation >= 256)
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// ? ((saturation_inc + saturation >= 256)
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? (65536 / saturation) - 256 : (65536 / (256 - saturation_inc)) - 256)
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// ? (65536 / saturation) - 256 : (65536 / (256 - saturation_inc)) - 256)
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: (saturation_inc);
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// : (saturation_inc);
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (reset) begin
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if (reset) begin
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calState <= 0;
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out_en <= 0;
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out_en <= 0;
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out_data[0] <= 0;
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out_data[0] <= 0;
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out_data[1] <= 0;
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out_data[1] <= 0;
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out_data[2] <= 0;
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out_data[2] <= 0;
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min <= 0;
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max <= 0;
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delta <= 0;
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value <= 0;
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light <= 0;
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saturation <= 0;
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alpha <= 0;
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data_cal[0] <= 0;
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data_cal[0] <= 0;
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data_cal[1] <= 0;
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data_cal[1] <= 0;
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data_cal[2] <= 0;
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data_cal[2] <= 0;
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@ -85,6 +96,32 @@ module SaturationCorrection #(
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CALC_DATA: begin
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CALC_DATA: begin
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if (enable) begin
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if (enable) begin
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if (calState == 0) begin
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max <= data_cache[0] > data_cache[1]?
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(data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]):
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(data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]);
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min <= data_cache[0] < data_cache[1]?
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(data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]):
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(data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]);
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calState <= 1;
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end else if (calState == 1) begin
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delta <= max - min;
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value <= max + min;
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calState <= 2;
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end else if (calState == 2) begin
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light <= value >>> 1;
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saturation <= (delta <<< 8) / max;
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calState <= 3;
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end else if (calState == 3) begin
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alpha <= (saturation_inc[31] == 0) ? ((saturation_inc + saturation >= 256)
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? (65536 / saturation) - 256 : (65536 / (256 - saturation_inc)) - 256)
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: (saturation_inc);
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calState <= 4;
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end else if (calState == 4) begin
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if (saturation_inc[31] == 0) begin
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if (saturation_inc[31] == 0) begin
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data_cal[0] <= (data_cache[0] << 8) + ((data_cache[0] - light) * alpha);
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data_cal[0] <= (data_cache[0] << 8) + ((data_cache[0] - light) * alpha);
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data_cal[1] <= (data_cache[1] << 8) + ((data_cache[1] - light) * alpha);
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data_cal[1] <= (data_cache[1] << 8) + ((data_cache[1] - light) * alpha);
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data_cal[1] <= (light << 8) + (data_cache[1] - light) * (256 + alpha);
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data_cal[1] <= (light << 8) + (data_cache[1] - light) * (256 + alpha);
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data_cal[2] <= (light << 8) + (data_cache[2] - light) * (256 + alpha);
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data_cal[2] <= (light << 8) + (data_cache[2] - light) * (256 + alpha);
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end
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end
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calState <= 5;
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end else begin
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calState <= 0;
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end
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end
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end
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end
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end
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SEND_DATA: begin
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SEND_DATA: begin
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if (in_ready) begin
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if (in_ready && !in_receive) begin
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out_en <= 1;
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out_en <= 1;
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if (enable && delta != 0) begin
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if (enable && delta != 0) begin
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out_data[0] <= (|data_cal[0][31:16]) ? 255 : (data_cal[0] > 0 ? data_cal[0][15:8] : 0);
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out_data[0] <= (|data_cal[0][31:16]) ? 255 : (data_cal[0] > 0 ? data_cal[0][15:8] : 0);
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@ -45,8 +45,8 @@ module Crop #(
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endcase
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endcase
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end
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end
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assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0;
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assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
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assign is_valid = ((OFFSET_Y <= cnt_y && cnt_y <= (OFFSET_Y + OUT_HEIGHT - 1)) &&
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assign is_valid = ((OFFSET_Y <= cnt_y && cnt_y <= (OFFSET_Y + OUT_HEIGHT - 1)) &&
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(OFFSET_X <= cnt_x && cnt_x <= (OFFSET_X + OUT_WIDTH))) ? 1 : 0;
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(OFFSET_X <= cnt_x && cnt_x <= (OFFSET_X + OUT_WIDTH))) ? 1 : 0;
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@ -59,9 +59,9 @@ module Demosaic2 #(
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end
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end
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// 请求数据
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// 请求数据
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assign out_ready = (cnt_data <= 2 && !in_en && state == READ_DATA) ? 1 : 0;
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assign out_ready = (cnt_data <= 2 && !in_en && state == READ_DATA && !reset) ? 1 : 0;
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// 收到数据
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// 收到数据
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assign out_receive = (in_en && state == READ_DATA) ? 1 : 0;
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assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
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// 各状态执行的操作
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// 各状态执行的操作
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always @(posedge clk) begin
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always @(posedge clk) begin
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7
isp.sv
7
isp.sv
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@ -22,7 +22,7 @@ module isp #(
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output wire out_en,
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output wire out_en,
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output wire [3 * COLOR_DEPTH - 1:0] out_data,
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output wire [3 * COLOR_DEPTH - 1:0] out_data,
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input wire in_ready,
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input wire in_ready,
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input wire in_receive,
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// input wire in_receive,
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// 颜色校正,低八位为小数位,高八位为整数位
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// 颜色校正,低八位为小数位,高八位为整数位
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input wire [15:0] gain_red,
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input wire [15:0] gain_red,
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wire saturation_en, saturation_ready, saturation_receive;
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wire saturation_en, saturation_ready, saturation_receive;
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wire [COLOR_DEPTH - 1 : 0] saturation_data[3];
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wire [COLOR_DEPTH - 1 : 0] saturation_data[3];
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// reg in_receive;
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// always @(posedge clk) in_receive <= in_en;
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wire in_receive;
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assign in_receive = ~in_ready;
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assign out_clk = clk;
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assign out_clk = clk;
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Demosaic2 #(
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Demosaic2 #(
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@ -57,7 +57,7 @@ SC_MODULE(TB_ISP) {
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sc_in<bool> im_clk;
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sc_in<bool> im_clk;
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sc_in<bool> im_en;
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sc_in<bool> im_en;
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sc_out<bool> out_ready;
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sc_out<bool> out_ready;
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sc_out<bool> out_receceive;
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// sc_out<bool> out_receceive;
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sc_in<uint32_t> im_data;
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sc_in<uint32_t> im_data;
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sc_out<bool> is_done;
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sc_out<bool> is_done;
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@ -117,7 +117,7 @@ SC_MODULE(TB_ISP) {
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while (true) {
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while (true) {
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if (im_en.read() && !is_finish) {
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if (im_en.read() && !is_finish) {
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out_ready.write(false);
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out_ready.write(false);
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out_receceive.write(true);
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// out_receceive.write(true);
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out[pos_y * OUT_WIDTH + pos_x] = im_data.read();
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out[pos_y * OUT_WIDTH + pos_x] = im_data.read();
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@ -135,7 +135,7 @@ SC_MODULE(TB_ISP) {
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}
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}
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} else {
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} else {
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out_ready.write(true);
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out_ready.write(true);
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out_receceive.write(false);
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// out_receceive.write(false);
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}
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}
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// when data didn't change some time, it end
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// when data didn't change some time, it end
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@ -315,7 +315,7 @@ int sc_main(int argc, char* argv[]) {
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sc_signal<bool> in_en;
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sc_signal<bool> in_en;
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sc_signal<bool> in_ready;
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sc_signal<bool> in_ready;
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sc_signal<bool> in_receive;
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// sc_signal<bool> in_receive;
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sc_signal<uint32_t> in_data[3];
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sc_signal<uint32_t> in_data[3];
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sc_signal<bool> out_clk;
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sc_signal<bool> out_clk;
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@ -351,7 +351,7 @@ int sc_main(int argc, char* argv[]) {
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isp->reset(reset);
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isp->reset(reset);
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isp->in_en(in_en);
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isp->in_en(in_en);
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isp->in_ready(in_ready);
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isp->in_ready(in_ready);
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isp->in_receive(in_receive);
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// isp->in_receive(in_receive);
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isp->in_data[0](in_data[0]);
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isp->in_data[0](in_data[0]);
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isp->in_data[1](in_data[1]);
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isp->in_data[1](in_data[1]);
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isp->in_data[2](in_data[2]);
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isp->in_data[2](in_data[2]);
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@ -410,7 +410,7 @@ int sc_main(int argc, char* argv[]) {
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tb_isp.in_receive(out_receive);
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tb_isp.in_receive(out_receive);
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tb_isp.out_en(in_en);
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tb_isp.out_en(in_en);
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tb_isp.out_ready(in_ready);
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tb_isp.out_ready(in_ready);
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tb_isp.out_receceive(in_receive);
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// tb_isp.out_receceive(in_receive);
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tb_isp.out_data[0](in_data[0]);
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tb_isp.out_data[0](in_data[0]);
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tb_isp.out_data[1](in_data[1]);
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tb_isp.out_data[1](in_data[1]);
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tb_isp.out_data[2](in_data[2]);
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tb_isp.out_data[2](in_data[2]);
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