diff --git a/Color/ColorBlender.sv b/Color/ColorBlender.sv index 2223507..5873b1a 100644 --- a/Color/ColorBlender.sv +++ b/Color/ColorBlender.sv @@ -51,8 +51,8 @@ module ColorBlender #( endcase end - assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0; - assign out_receive = (in_en && state == READ_DATA) ? 1 : 0; + assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0; + assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0; always @(posedge clk) begin if (reset) begin diff --git a/Color/GammaCorrection2.sv b/Color/GammaCorrection2.sv index b83f289..f5aa817 100644 --- a/Color/GammaCorrection2.sv +++ b/Color/GammaCorrection2.sv @@ -38,8 +38,8 @@ module GammaCorrection2 #( endcase end - assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0; - assign out_receive = (in_en && state == READ_DATA) ? 1 : 0; + assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0; + assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0; always @(posedge clk) begin if (reset) begin @@ -62,7 +62,7 @@ module GammaCorrection2 #( end SEND_DATA: begin - if (in_ready) begin + if (in_ready && !in_receive) begin out_en <= 1; if (enable) begin out_data[0] <= gamma_table[data_cache[0]]; diff --git a/Color/GreyWorld.sv b/Color/GreyWorld.sv index 1a8fb21..e0dc1db 100644 --- a/Color/GreyWorld.sv +++ b/Color/GreyWorld.sv @@ -51,8 +51,8 @@ module GreyWorld #( endcase end - assign out_ready = (!in_en && !reset) ? 1 : 0; - assign out_receive = (in_en && !reset) ? 1 : 0; + assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0; + assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0; assign average = ((red_total + green_total + blue_total) << 8) / (3 * IM_SIZE); diff --git a/Color/SaturationCorrection.sv b/Color/SaturationCorrection.sv index c1c0831..7eedf67 100644 --- a/Color/SaturationCorrection.sv +++ b/Color/SaturationCorrection.sv @@ -19,13 +19,14 @@ module SaturationCorrection #( input wire enable, input wire signed [31:0] saturation_inc ); - reg [2:0] state, nextState; + reg [2:0] state, nextState, calState; localparam reg [2:0] READ_DATA = 0; localparam reg [2:0] CALC_DATA = 1; localparam reg [2:0] SEND_DATA = 2; reg signed [31:0] data_cal[3], data_cache[3]; - wire signed [31:0] max, min, delta, value, light, saturation, alpha; + // wire signed [31:0] max, min, delta, value, light, saturation, alpha; + reg signed [31:0] max, min, delta, value, light, saturation, alpha; always @(posedge clk) begin if (reset) state <= READ_DATA; @@ -34,39 +35,49 @@ module SaturationCorrection #( always @(*) begin case (state) - READ_DATA: nextState = in_en ? CALC_DATA : READ_DATA; - CALC_DATA: nextState = SEND_DATA; + READ_DATA: nextState = in_en ? 3 : READ_DATA; + 3: nextState = CALC_DATA; + CALC_DATA: nextState = (calState >= 5 || !enable) ? SEND_DATA : CALC_DATA; SEND_DATA: nextState = in_receive ? READ_DATA : SEND_DATA; default: nextState = READ_DATA; endcase end - assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0; - assign out_receive = (in_en && state == READ_DATA) ? 1 : 0; + assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0; + assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0; - assign max = data_cache[0] > data_cache[1]? - (data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]): - (data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]); - assign min = data_cache[0] < data_cache[1]? - (data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]): - (data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]); - assign delta = max - min; - assign value = max + min; - assign light = value >>> 1; - // assign saturation = (light <= 128) ? (delta <<< 8) / value : (delta <<< 8) / (512 - value); - assign saturation = (delta <<< 8) / max; - assign alpha = (saturation_inc[31] == 0) - ? ((saturation_inc + saturation >= 256) - ? (65536 / saturation) - 256 : (65536 / (256 - saturation_inc)) - 256) - : (saturation_inc); + // assign max = data_cache[0] > data_cache[1]? + // (data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]): + // (data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]); + // assign min = data_cache[0] < data_cache[1]? + // (data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]): + // (data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]); + // assign delta = max - min; + // assign value = max + min; + // assign light = value >>> 1; + // // // assign saturation = (light <= 128) ? (delta <<< 8) / value : (delta <<< 8) / (512 - value); + // assign saturation = (delta <<< 8) / max; + // assign alpha = (saturation_inc[31] == 0) + // ? ((saturation_inc + saturation >= 256) + // ? (65536 / saturation) - 256 : (65536 / (256 - saturation_inc)) - 256) + // : (saturation_inc); always @(posedge clk) begin if (reset) begin + calState <= 0; out_en <= 0; out_data[0] <= 0; out_data[1] <= 0; out_data[2] <= 0; + min <= 0; + max <= 0; + delta <= 0; + value <= 0; + light <= 0; + saturation <= 0; + alpha <= 0; + data_cal[0] <= 0; data_cal[1] <= 0; data_cal[2] <= 0; @@ -85,20 +96,51 @@ module SaturationCorrection #( CALC_DATA: begin if (enable) begin - if (saturation_inc[31] == 0) begin - data_cal[0] <= (data_cache[0] << 8) + ((data_cache[0] - light) * alpha); - data_cal[1] <= (data_cache[1] << 8) + ((data_cache[1] - light) * alpha); - data_cal[2] <= (data_cache[2] << 8) + ((data_cache[2] - light) * alpha); + if (calState == 0) begin + max <= data_cache[0] > data_cache[1]? + (data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]): + (data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]); + min <= data_cache[0] < data_cache[1]? + (data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]): + (data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]); + + calState <= 1; + end else if (calState == 1) begin + delta <= max - min; + value <= max + min; + + calState <= 2; + end else if (calState == 2) begin + light <= value >>> 1; + saturation <= (delta <<< 8) / max; + + calState <= 3; + end else if (calState == 3) begin + alpha <= (saturation_inc[31] == 0) ? ((saturation_inc + saturation >= 256) + ? (65536 / saturation) - 256 : (65536 / (256 - saturation_inc)) - 256) + : (saturation_inc); + + calState <= 4; + end else if (calState == 4) begin + if (saturation_inc[31] == 0) begin + data_cal[0] <= (data_cache[0] << 8) + ((data_cache[0] - light) * alpha); + data_cal[1] <= (data_cache[1] << 8) + ((data_cache[1] - light) * alpha); + data_cal[2] <= (data_cache[2] << 8) + ((data_cache[2] - light) * alpha); + end else begin + data_cal[0] <= (light << 8) + (data_cache[0] - light) * (256 + alpha); + data_cal[1] <= (light << 8) + (data_cache[1] - light) * (256 + alpha); + data_cal[2] <= (light << 8) + (data_cache[2] - light) * (256 + alpha); + end + + calState <= 5; end else begin - data_cal[0] <= (light << 8) + (data_cache[0] - light) * (256 + alpha); - data_cal[1] <= (light << 8) + (data_cache[1] - light) * (256 + alpha); - data_cal[2] <= (light << 8) + (data_cache[2] - light) * (256 + alpha); + calState <= 0; end end end SEND_DATA: begin - if (in_ready) begin + if (in_ready && !in_receive) begin out_en <= 1; if (enable && delta != 0) begin out_data[0] <= (|data_cal[0][31:16]) ? 255 : (data_cal[0] > 0 ? data_cal[0][15:8] : 0); diff --git a/Crop/Crop.sv b/Crop/Crop.sv index 8ee80c1..832ac92 100644 --- a/Crop/Crop.sv +++ b/Crop/Crop.sv @@ -45,8 +45,8 @@ module Crop #( endcase end - assign out_ready = (!in_en && state == READ_DATA) ? 1 : 0; - assign out_receive = (in_en && state == READ_DATA) ? 1 : 0; + assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0; + assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0; assign is_valid = ((OFFSET_Y <= cnt_y && cnt_y <= (OFFSET_Y + OUT_HEIGHT - 1)) && (OFFSET_X <= cnt_x && cnt_x <= (OFFSET_X + OUT_WIDTH))) ? 1 : 0; diff --git a/Demosaic/Demosaic2.sv b/Demosaic/Demosaic2.sv index ff49849..eae5640 100644 --- a/Demosaic/Demosaic2.sv +++ b/Demosaic/Demosaic2.sv @@ -59,9 +59,9 @@ module Demosaic2 #( end // 请求数据 - assign out_ready = (cnt_data <= 2 && !in_en && state == READ_DATA) ? 1 : 0; + assign out_ready = (cnt_data <= 2 && !in_en && state == READ_DATA && !reset) ? 1 : 0; // 收到数据 - assign out_receive = (in_en && state == READ_DATA) ? 1 : 0; + assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0; // 各状态执行的操作 always @(posedge clk) begin diff --git a/isp.sv b/isp.sv index 19540a9..306cf9a 100644 --- a/isp.sv +++ b/isp.sv @@ -22,7 +22,7 @@ module isp #( output wire out_en, output wire [3 * COLOR_DEPTH - 1:0] out_data, input wire in_ready, - input wire in_receive, + // input wire in_receive, // 颜色校正，低八位为小数位，高八位为整数位 input wire [15:0] gain_red, @@ -70,6 +70,11 @@ module isp #( wire saturation_en, saturation_ready, saturation_receive; wire [COLOR_DEPTH - 1 : 0] saturation_data[3]; + // reg in_receive; + // always @(posedge clk) in_receive <= in_en; + wire in_receive; + assign in_receive = ~in_ready; + assign out_clk = clk; Demosaic2 #( diff --git a/sim/sc_main.cpp b/sim/sc_main.cpp index fe93142..51db897 100644 --- a/sim/sc_main.cpp +++ b/sim/sc_main.cpp @@ -57,7 +57,7 @@ SC_MODULE(TB_ISP) { sc_in im_clk; sc_in im_en; sc_out out_ready; - sc_out out_receceive; + // sc_out out_receceive; sc_in im_data; sc_out is_done; @@ -117,7 +117,7 @@ SC_MODULE(TB_ISP) { while (true) { if (im_en.read() && !is_finish) { out_ready.write(false); - out_receceive.write(true); + // out_receceive.write(true); out[pos_y * OUT_WIDTH + pos_x] = im_data.read(); @@ -135,7 +135,7 @@ SC_MODULE(TB_ISP) { } } else { out_ready.write(true); - out_receceive.write(false); + // out_receceive.write(false); } // when data didn't change some time, it end @@ -315,7 +315,7 @@ int sc_main(int argc, char* argv[]) { sc_signal in_en; sc_signal in_ready; - sc_signal in_receive; + // sc_signal in_receive; sc_signal in_data[3]; sc_signal out_clk; @@ -351,7 +351,7 @@ int sc_main(int argc, char* argv[]) { isp->reset(reset); isp->in_en(in_en); isp->in_ready(in_ready); - isp->in_receive(in_receive); + // isp->in_receive(in_receive); isp->in_data[0](in_data[0]); isp->in_data[1](in_data[1]); isp->in_data[2](in_data[2]); @@ -410,7 +410,7 @@ int sc_main(int argc, char* argv[]) { tb_isp.in_receive(out_receive); tb_isp.out_en(in_en); tb_isp.out_ready(in_ready); - tb_isp.out_receceive(in_receive); + // tb_isp.out_receceive(in_receive); tb_isp.out_data[0](in_data[0]); tb_isp.out_data[1](in_data[1]); tb_isp.out_data[2](in_data[2]);