SikongJueluo/ISP
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix DPC and reconstruct isp

Browse Source
This commit is contained in:
SikongJueluo
2024-11-03 20:38:29 +08:00
parent a8fa609228
commit 42f6cdbbda
41 changed files with 25742 additions and 693 deletions
Download Patch File Download Diff File Expand all files Collapse all files

319
rtl/BayerProcess/DPC.sv
View File

@@ -1,30 +1,31 @@
`timescale 1ns / 1ps
module DPC #(
parameter reg [15:0] TOTAL_WIDTH = 512 + 3, // 总图像宽度
parameter reg [15:0] TOTAL_HEIGHT = 256 + 3, // 总图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
parameter reg [ 4:0] MODULE_ENABLE = 0, // 是否启用该模块，DEBUG用
parameter reg [ 4:0] LABLE_ENABLE = 1 // 是否启动坏点标注，DEBUG用
) (
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
parameter reg signed [15:0] THRESHOLD = 30, // 阈值
parameter reg [ 4:0] MODULE_ENABLE = 0, // 是否启用该模块，DEBUG用
parameter reg [ 4:0] LABLE_ENABLE= 1 // 0:不启用标注, 1:启用标注, 2:启用方向标注
)(
input wire clk,
input wire reset,
input wire [DATA_WIDTH - 1:0] in_data [5*5],
output reg [DATA_WIDTH - 1:0] out_data,
input wire in_valid,
input wire [DATA_WIDTH - 1:0] in_data [5*5],
input wire [7:0] in_user,
output reg [DATA_WIDTH - 1:0] out_data,
output wire [7:0] out_user,
input wire in_valid,
output wire out_valid,
input wire in_ready,
input wire in_ready,
output wire out_ready
);
localparam WINDOW_LENGTH = 5;
localparam DATA_NUM = WINDOW_LENGTH * WINDOW_LENGTH;
localparam EXPAND_BITS = 5;
localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH;
localparam EXPAND_BITS = 1;
localparam PIPILINE = 9;
reg [7:0] pipeline_user[PIPILINE];
reg [PIPILINE-1:0] pipeline_valid;
wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
@@ -33,97 +34,90 @@ module DPC #(
assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = pipeline_valid[PIPILINE-1];
assign out_user = pipeline_user[PIPILINE-1];
reg [DATA_WIDTH-1:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [DATA_WIDTH-1:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [DATA_WIDTH-1:0] channel_cache[9]; // 缓存颜色通道数据，channel_cache[4]就是中心像素点
reg [DATA_WIDTH-1:0]
channel_cache0,
channel_cache1,
channel_cache2,
channel_cache3,
channel_cache4; // 缓存中心像素点的颜色数据
reg signed [DATA_WIDTH-1+EXPAND_BITS:0]
grad_h_cache[3], grad_v_cache[3], grad_45_cache[3], grad_135_cache[3];
reg [DATA_WIDTH-1+EXPAND_BITS:0]
grad_h_cache0[3], grad_v_cache0[3], grad_45_cache0[3], grad_135_cache0[3];
reg [DATA_WIDTH-1+EXPAND_BITS:0]
grad_h_cache1[3], grad_v_cache1[3], grad_45_cache1[3], grad_135_cache1[3];
reg [DATA_WIDTH-1+EXPAND_BITS:0]
grad_h_cache2[3], grad_v_cache2[3], grad_45_cache2[3], grad_135_cache2[3];
reg [DATA_WIDTH-1+EXPAND_BITS:0] grad_median_cache[4];
reg [1:0] flag_which_dict;
reg [DATA_WIDTH-1:0]
channel_cache_correct[4],
channel_cache_correct0[4],
channel_cache_correct1[4],
channel_cache_correct2[4];
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache[9]; // 缓存颜色通道数据，channel_cache[4]就是中心像素点
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache0,channel_cache1,channel_cache2,channel_cache3,channel_cache4; // 缓存中心像素点的颜色数据
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache[3], grad_v_cache[3], grad_i_cache[3], grad_t_cache[3];
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache0[3], grad_v_cache0[3], grad_i_cache0[3], grad_t_cache0[3];
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_h_cache1[3], grad_v_cache1[3], grad_i_cache1[3], grad_t_cache1[3];
reg signed [DATA_WIDTH-1+EXPAND_BITS+2:0] grad_cache_excute[4];
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_cache_center[4];
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] channel_cache_correct[4], channel_cache_correct1[4], channel_cache_correct2[4];
reg signed [DATA_WIDTH-1+EXPAND_BITS+EXPAND_BITS:0] channel_cache_correct0[4];
reg signed [DATA_WIDTH-1+EXPAND_BITS:0] grad_median_cache[4];
reg [1:0] flag_which_dict, dic2;
reg [DATA_WIDTH-1:0] channel_cache_correct_final;
reg flag_if_need_corection;
reg [15:0] pos_x;
reg pos_y_bit;
reg pos_x, pos_y;
reg [1:0] raw_type;
/*
-------h
|\ i
| \/
| /\
|/ \
v t
*/
integer i;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= 0;
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= 0;
for (i = 0; i < 9; i = i + 1) channel_cache[i] <= 0;
if(reset) begin
for(i=0;i<PIPILINE;i=i+1) pipeline_user[i] <= 0;
for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= 0;
for(i=0;i<DATA_NUM;i=i+1) data_cache0[i] <= 0;
for(i=0;i<9;i=i+1) channel_cache[i] <= 0;
channel_cache0 <= 0;
channel_cache1 <= 0;
channel_cache2 <= 0;
channel_cache3 <= 0;
channel_cache4 <= 0;
channel_cache_correct_final <= 0;
for (i = 0; i < 3; i = i + 1) grad_h_cache[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_h_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_h_cache2[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_v_cache[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_v_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_v_cache2[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_45_cache[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_45_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_45_cache2[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_135_cache[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_135_cache1[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_135_cache2[i] <= 0;
for (i = 0; i < 3; i = i + 1) grad_median_cache[i] <= 0;
for(i=0;i<3;i=i+1) grad_h_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_h_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_h_cache1[i] <= 0; for(i=0;i<3;i=i+1);
for(i=0;i<3;i=i+1) grad_v_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_v_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_v_cache1[i] <= 0; for(i=0;i<3;i=i+1);
for(i=0;i<3;i=i+1) grad_i_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_i_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_i_cache1[i] <= 0; for(i=0;i<3;i=i+1);
for(i=0;i<3;i=i+1) grad_t_cache[i] <= 0; for(i=0;i<3;i=i+1) grad_t_cache0[i] <= 0; for(i=0;i<3;i=i+1) grad_t_cache1[i] <= 0; for(i=0;i<3;i=i+1);
for(i=0;i<3;i=i+1) grad_median_cache[i] <= 0;
for(i=0;i<4;i=i+1) grad_cache_excute[i] <= 0;
for(i=0;i<4;i=i+1) grad_cache_center[i] <= 0;
flag_which_dict <= 0;
flag_if_need_corection <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct[i] <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct1[i] <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct0[i] <= 0;
for (i = 0; i < 4; i = i + 1) channel_cache_correct2[i] <= 0;
for(i=0;i<4;i=i+1) channel_cache_correct[i] <= 0; for(i=0;i<4;i=i+1) channel_cache_correct1[i] <= 0;
for(i=0;i<4;i=i+1) channel_cache_correct0[i] <= 0;for(i=0;i<4;i=i+1) channel_cache_correct2[i] <= 0;
pipeline_valid <= 0;
out_data <= 0;
pos_x <= ~0;
pos_y_bit <= ~0;
pos_x <= 0;
pos_y <= 0;
raw_type <= RAW_TYPE;
end else if (pipeline_running) begin
end else if(pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if (in_valid) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= in_data[i];
pos_x <= (pos_x >= TOTAL_WIDTH - 1) ? (0) : (pos_x + 1);
pos_y_bit <= (pos_x >= TOTAL_WIDTH - 1) ? (~pos_y_bit) : (pos_y_bit);
if(in_valid) begin
for(i=0;i<DATA_NUM;i=i+1) data_cache0[i] <= {{(EXPAND_BITS){1'b0}},in_data[i]};
pipeline_user[0] <= in_user;
pos_x <= (in_user[0])?(0):(~pos_x);
pos_y <= (in_user[0])?((in_user[1])?(0):(~pos_y)):(pos_y);
end
if (pipeline_valid[0]) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= data_cache0[i];
if(pipeline_valid[0]) begin
for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= data_cache0[i];
pipeline_user[1] <= pipeline_user[0];
case (RAW_TYPE)
2'b00: raw_type <= {pos_y_bit, pos_x[0]};
2'b01: raw_type <= {pos_y_bit, ~pos_x[0]};
2'b10: raw_type <= {~pos_y_bit, pos_x[0]};
2'b11: raw_type <= {~pos_y_bit, ~pos_x[0]};
2'b00: raw_type <= { pos_y, pos_x};
2'b01: raw_type <= { pos_y, ~pos_x};
2'b10: raw_type <= {~pos_y, pos_x};
2'b11: raw_type <= {~pos_y, ~pos_x};
endcase
end
if (pipeline_valid[1]) begin
if(pipeline_valid[1]) begin
pipeline_user[2] <= pipeline_user[1];
case (raw_type)
1, 2: begin
1,2: begin
channel_cache[0] <= data_cache[00];
channel_cache[1] <= data_cache[10];
channel_cache[2] <= data_cache[20];
@@ -134,7 +128,7 @@ module DPC #(
channel_cache[7] <= data_cache[14];
channel_cache[8] <= data_cache[24];
end
0, 3: begin
0,3: begin
channel_cache[0] <= data_cache[02];
channel_cache[1] <= data_cache[06];
channel_cache[2] <= data_cache[10];
@@ -148,115 +142,125 @@ module DPC #(
endcase
end
if (pipeline_valid[2]) begin //计算梯度，同时开始校正后数据的部分计算
channel_cache0 <= channel_cache[4];
if(pipeline_valid[2]) begin //计算梯度，同时开始校正后数据的部分计算
pipeline_user[3] <= pipeline_user[2];
channel_cache0 <= channel_cache[4];
grad_h_cache[0] <= channel_cache[0] + channel_cache[2] - 2 * channel_cache[1];
grad_h_cache[1] <= channel_cache[3] + channel_cache[5] - 2 * channel_cache[4];
grad_h_cache[2] <= channel_cache[6] + channel_cache[8] - 2 * channel_cache[7];
grad_v_cache[0] <= channel_cache[0] + channel_cache[6] - 2 * channel_cache[3];
grad_v_cache[1] <= channel_cache[1] + channel_cache[7] - 2 * channel_cache[4];
grad_v_cache[2] <= channel_cache[2] + channel_cache[8] - 2 * channel_cache[5];
grad_45_cache[0] <= 2 * (channel_cache[1] - channel_cache[3]);
grad_45_cache[1] <= channel_cache[6] + channel_cache[2] - 2 * channel_cache[4];
grad_45_cache[2] <= 2 * (channel_cache[7] - channel_cache[5]);
grad_135_cache[0] <= 2 * (channel_cache[1] - channel_cache[5]);
grad_135_cache[1] <= channel_cache[0] + channel_cache[8] - 2 * channel_cache[4];
grad_135_cache[2] <= 2 * (channel_cache[3] - channel_cache[7]);
grad_h_cache[0] <= channel_cache[0]/2 + channel_cache[2]/2 - channel_cache[1];
grad_h_cache[1] <= channel_cache[3]/2 + channel_cache[5]/2 - channel_cache[4];
grad_h_cache[2] <= channel_cache[6]/2 + channel_cache[8]/2 - channel_cache[7];
grad_v_cache[0] <= channel_cache[0]/2 + channel_cache[6]/2 - channel_cache[3];
grad_v_cache[1] <= channel_cache[1]/2 + channel_cache[7]/2 - channel_cache[4];
grad_v_cache[2] <= channel_cache[2]/2 + channel_cache[8]/2 - channel_cache[5];
grad_i_cache[0] <= channel_cache[1]/2 - channel_cache[3]/2;
grad_i_cache[1] <= channel_cache[6]/2 + channel_cache[2]/2 - channel_cache[4];
grad_i_cache[2] <= channel_cache[5]/2 - channel_cache[7]/2;
grad_t_cache[0] <= channel_cache[1]/2 - channel_cache[5]/2;
grad_t_cache[1] <= channel_cache[0]/2 + channel_cache[8]/2 - channel_cache[4];
grad_t_cache[2] <= channel_cache[3]/2 - channel_cache[7]/2;
channel_cache_correct[0] <= channel_cache[3] / 2 + channel_cache[5] / 2;
channel_cache_correct[1] <= channel_cache[1] / 2 + channel_cache[7] / 2;
channel_cache_correct[2] <= channel_cache[2] / 2 + channel_cache[6] / 2;
channel_cache_correct[3] <= channel_cache[0] / 2 + channel_cache[8] / 2;
channel_cache_correct[0] <= channel_cache[3]/2 + channel_cache[5]/2;
channel_cache_correct[1] <= channel_cache[1]/2 + channel_cache[7]/2;
channel_cache_correct[2] <= channel_cache[2]/2 + channel_cache[6]/2;
channel_cache_correct[3] <= channel_cache[0]/2 + channel_cache[8]/2;
end
if(pipeline_valid[3]) begin //计算绝对值，同时完成校正后数据的计算,注意grad_h_cache等是singed，可能为负数
channel_cache1 <= channel_cache0;
if(pipeline_valid[3]) begin //计算绝对值，同时完成校正后数据的计算
pipeline_user[4] <= pipeline_user[3];
channel_cache1 <= channel_cache0;
grad_h_cache0 [0] <= grad_h_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [0] + 1) : (grad_h_cache [0]);
grad_h_cache0 [1] <= grad_h_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [1] + 1) : (grad_h_cache [1]);
grad_h_cache0 [2] <= grad_h_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_h_cache [2] + 1) : (grad_h_cache [2]);
grad_v_cache0 [0] <= grad_v_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [0] + 1) : (grad_v_cache [0]);
grad_v_cache0 [1] <= grad_v_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [1] + 1) : (grad_v_cache [1]);
grad_v_cache0 [2] <= grad_v_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_v_cache [2] + 1) : (grad_v_cache [2]);
grad_45_cache0 [0] <= grad_45_cache [0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [0] + 1) : (grad_45_cache [0]);
grad_45_cache0 [1] <= grad_45_cache [1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [1] + 1) : (grad_45_cache [1]);
grad_45_cache0 [2] <= grad_45_cache [2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_45_cache [2] + 1) : (grad_45_cache [2]);
grad_135_cache0[0] <= grad_135_cache[0][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[0] + 1) : (grad_135_cache[0]);
grad_135_cache0[1] <= grad_135_cache[1][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[1] + 1) : (grad_135_cache[1]);
grad_135_cache0[2] <= grad_135_cache[2][DATA_WIDTH-1+EXPAND_BITS] ? (~grad_135_cache[2] + 1) : (grad_135_cache[2]);
channel_cache_correct0[0] <= channel_cache_correct[0] + grad_h_cache[0]/4 + grad_h_cache[2]/4;
channel_cache_correct0[1] <= channel_cache_correct[1] + grad_v_cache[0]/4 + grad_v_cache[2]/4;
channel_cache_correct0[2] <= channel_cache_correct[2] + grad_45_cache[0]/4 + grad_45_cache[2]/4;
channel_cache_correct0[3] <= channel_cache_correct[3] + grad_135_cache[0]/4 + grad_135_cache[2]/4;
for(i=0;i<3;i=i+1) grad_h_cache0[i] <= (grad_h_cache[i] < 0) ? (-grad_h_cache[i]) : (grad_h_cache[i]);
for(i=0;i<3;i=i+1) grad_v_cache0[i] <= (grad_v_cache[i] < 0) ? (-grad_v_cache[i]) : (grad_v_cache[i]);
for(i=0;i<3;i=i+1) grad_i_cache0[i] <= (grad_i_cache[i] < 0) ? (-grad_i_cache[i]) : (grad_i_cache[i]);
for(i=0;i<3;i=i+1) grad_t_cache0[i] <= (grad_t_cache[i] < 0) ? (-grad_t_cache[i]) : (grad_t_cache[i]);
channel_cache_correct0[0] <= channel_cache_correct[0] - grad_h_cache[0]/2 - grad_h_cache[2]/2;
channel_cache_correct0[1] <= channel_cache_correct[1] - grad_v_cache[0]/2 - grad_v_cache[2]/2;
channel_cache_correct0[2] <= channel_cache_correct[2] - grad_i_cache[0]/2 - grad_i_cache[2]/2;
channel_cache_correct0[3] <= channel_cache_correct[3] - grad_t_cache[0]/2 - grad_t_cache[2]/2;
end
if (pipeline_valid[4]) begin //计算中位数
if(pipeline_valid[4]) begin //计算中位数
pipeline_user[5] <= pipeline_user[4];
channel_cache2 <= channel_cache1;
for (i = 0; i < 4; i = i + 1) channel_cache_correct1[i] <= channel_cache_correct0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_h_cache1[i] <= grad_h_cache0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_v_cache1[i] <= grad_v_cache0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_45_cache1[i] <= grad_45_cache0[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_135_cache1[i] <= grad_135_cache0[i];
for(i=0;i<4;i=i+1) channel_cache_correct1[i] <= (channel_cache_correct0[i] < 0) ? (0) : (channel_cache_correct0[i]);
// for(i=0;i<4;i=i+1) channel_cache_correct1[i] <= channel_cache_correct0[i];
for(i=0;i<3;i=i+1) grad_h_cache1[i] <= grad_h_cache0[i];
for(i=0;i<3;i=i+1) grad_v_cache1[i] <= grad_v_cache0[i];
for(i=0;i<3;i=i+1) grad_i_cache1[i] <= grad_i_cache0[i];
for(i=0;i<3;i=i+1) grad_t_cache1[i] <= grad_t_cache0[i];
grad_median_cache[0] <= MEDIAN(grad_h_cache0);
grad_median_cache[1] <= MEDIAN(grad_v_cache0);
grad_median_cache[2] <= MEDIAN(grad_45_cache0);
grad_median_cache[3] <= MEDIAN(grad_135_cache0);
grad_median_cache[2] <= MEDIAN(grad_i_cache0);
grad_median_cache[3] <= MEDIAN(grad_t_cache0);
end
if (pipeline_valid[5]) begin //计算最小值，判断最小梯度方向
if(pipeline_valid[5]) begin //计算最小值，判断最小梯度方向
pipeline_user[6] <= pipeline_user[5];
channel_cache3 <= channel_cache2;
for (i = 0; i < 4; i = i + 1) channel_cache_correct2[i] <= channel_cache_correct1[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_h_cache2[i] <= grad_h_cache1[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_v_cache2[i] <= grad_v_cache1[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_45_cache2[i] <= grad_45_cache1[i];
for (i = 0; i < 3 + EXPAND_BITS; i = i + 1) grad_135_cache2[i] <= grad_135_cache1[i];
for(i=0;i<4;i=i+1) channel_cache_correct2[i] <= channel_cache_correct1[i];
grad_cache_center[0] <= grad_h_cache1[1]/4;
grad_cache_center[1] <= grad_v_cache1[1]/4;
grad_cache_center[2] <= grad_i_cache1[1]/4;
grad_cache_center[3] <= grad_t_cache1[1]/4;
grad_cache_excute[0] <= grad_h_cache1[0] + grad_h_cache1[2] + THRESHOLD;
grad_cache_excute[1] <= grad_v_cache1[0] + grad_v_cache1[2] + THRESHOLD;
grad_cache_excute[2] <= grad_i_cache1[0] + grad_i_cache1[2] + THRESHOLD;
grad_cache_excute[3] <= grad_t_cache1[0] + grad_t_cache1[2] + THRESHOLD;
flag_which_dict <= MIN(grad_median_cache);
end
if (pipeline_valid[6]) begin //在最小梯度方向上判断中心点是否是坏点
if(pipeline_valid[6]) begin //在最小梯度方向上判断中心点是否是坏点
pipeline_user[7] <= pipeline_user[6];
dic2 <= flag_which_dict;
channel_cache4 <= channel_cache3;
channel_cache_correct_final <= channel_cache_correct2[flag_which_dict];
channel_cache_correct_final <= channel_cache_correct2[flag_which_dict][DATA_WIDTH-1:0];
case (flag_which_dict)
2'b00:
flag_if_need_corection <= grad_h_cache2[1] / 4 > (grad_h_cache2[0] + grad_h_cache2[2]);
2'b01:
flag_if_need_corection <= grad_v_cache2[1] / 4 > (grad_v_cache2[0] + grad_v_cache2[2]);
2'b10:
flag_if_need_corection <= grad_45_cache2[1] / 4 > (grad_45_cache2[0] + grad_45_cache2[2]);
2'b11:
flag_if_need_corection <= grad_135_cache2[1]/4 > (grad_135_cache2[0] + grad_135_cache2[2]);
2'b00, 2'b01: flag_if_need_corection <= (grad_cache_center[flag_which_dict] > grad_cache_excute[flag_which_dict]);
2'b10, 2'b11: flag_if_need_corection <= (grad_cache_center[2] > grad_cache_excute[2]) && ((grad_cache_center[3] > grad_cache_excute[3]));
endcase
end
if(pipeline_valid[7]) begin //如果是坏点，输出计算后的值；如果不是坏点，输出原值
if (MODULE_ENABLE)
out_data <= (flag_if_need_corection)?((LABLE_ENABLE)?(12'hFFF):(channel_cache_correct_final)):(channel_cache4);
else out_data <= channel_cache4;
// if(flag_if_need_corection == 1'b1 && channel_cache_correct_final == 0) $stop;
pipeline_user[8] <= pipeline_user[7];
if(MODULE_ENABLE) begin
case(LABLE_ENABLE)
0: out_data <= (flag_if_need_corection)?(channel_cache_correct_final):(channel_cache4);
1: out_data <= (flag_if_need_corection)?(12'hFFF):(channel_cache4);
2: begin
case(dic2)
2'b00: out_data <= (12'h00F);
2'b01: out_data <= (12'h0F0);
2'b10: out_data <= (12'hF00);
2'b11: out_data <= (12'h0FF);
endcase
end
endcase
end else out_data <= channel_cache4;
end
end
end
function [DATA_WIDTH-1+EXPAND_BITS:0] MEDIAN;
input [DATA_WIDTH-1+EXPAND_BITS:0] inx[3];
begin
if ((inx[0] >= inx[1] && inx[1] >= inx[2]) || (inx[2] >= inx[1] && inx[1] >= inx[0]))
MEDIAN = inx[1];
else if ((inx[1] >= inx[0]) || (inx[0] >= inx[1])) MEDIAN = inx[0];
function signed [DATA_WIDTH-1+EXPAND_BITS:0] MEDIAN;
input signed [DATA_WIDTH-1+EXPAND_BITS:0] inx[3];
begin
if((inx[0] >= inx[1] && inx[1] >= inx[2]) || (inx[2] >= inx[1] && inx[1] >= inx[0])) MEDIAN = inx[1];
else if((inx[1] >= inx[0] && inx[0] >= inx[2]) || (inx[2] >= inx[0] && inx[0] >= inx[1])) MEDIAN = inx[0];
else MEDIAN = inx[2];
end
end
endfunction
function [1:0] MIN;
input [DATA_WIDTH-1+EXPAND_BITS:0] inx[4];
begin
if (inx[0] >= inx[1] && inx[0] >= inx[2] && inx[0] >= inx[3]) MIN = 2'b00;
else if (inx[1] >= inx[0] && inx[1] >= inx[2] && inx[1] >= inx[3]) MIN = 2'b01;
else if (inx[2] >= inx[0] && inx[2] >= inx[1] && inx[2] >= inx[3]) MIN = 2'b10;
input signed [DATA_WIDTH-1+EXPAND_BITS:0] inx[4];
begin
if(inx[0] <= inx[1] && inx[0] <= inx[2] && inx[0] <= inx[3]) MIN = 2'b00;
else if(inx[1] <= inx[2] && inx[1] <= inx[3]) MIN = 2'b01;
else if(inx[2] <= inx[3]) MIN = 2'b10;
else MIN = 2'b11;
end
end
endfunction
/*
@@ -299,4 +303,3 @@ module DPC #(
endmodule

1
rtl/BayerProcess/Demosaic2.sv
View File

@@ -1,4 +1,3 @@
`timescale 1ns/1ps
module Demosaic2 #(
parameter reg [15:0] IM_WIDTH = 512, // 图像宽度
parameter reg [15:0] IM_HEIGHT = 256, // 图像高度

137
rtl/BayerProcess/Demosaic_Pipeline.sv
View File

@@ -1,31 +1,28 @@
`timescale 1ns / 1ps
module Demosaic_Pipeline #(
parameter WINDOW_LENGTH = 3,
parameter reg [15:0] TOTAL_WIDTH = 512 + 3, // 总图像宽度
parameter reg [15:0] TOTAL_HEIGHT = 256 + 3, // 总图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
) (
parameter WINDOW_LENGTH = 3,
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
)(
input wire clk,
input wire reset,
input wire [DATA_WIDTH - 1:0] in_data [WINDOW_LENGTH*WINDOW_LENGTH], // 数据输入线.第一列数据在[0],[1],[2]中
output reg [DATA_WIDTH - 1:0] out_data[3], // 数据输出线，3、2、1分别表示r、g、b
input wire [7:0] in_user,
output reg [DATA_WIDTH - 1:0] out_data [3], // 数据输出线，3、2、1分别表示r、g、b
output wire [7:0] out_user,
input wire in_valid,
input wire in_valid,
output wire out_valid,
input wire in_ready,
output wire out_ready,
output reg out_hsync, // 行同步，一行第一个像素点输出的同时高电平
output reg out_fsync // 帧同步，一帧第一个像素点输出的同时高电平
input wire in_ready,
output wire out_ready
);
localparam DATA_NUM = WINDOW_LENGTH * WINDOW_LENGTH;
localparam PIPILINE = 4;
localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH;
localparam PIPILINE = 2;
reg [PIPILINE-1:0] pipeline_valid;
reg [7:0] pipeline_user[PIPILINE];
wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
@@ -33,89 +30,71 @@ module Demosaic_Pipeline #(
assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = pipeline_valid[PIPILINE-1];
assign out_user = pipeline_user[PIPILINE-1];
reg [DATA_WIDTH-1:0] data_cache [DATA_NUM]; // 缓存颜色数据，行列nxn
reg [DATA_WIDTH-1:0] data_cache0[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [31:0] pos_x, pos_y, temp_pos_x1, temp_pos_y1, temp_pos_x2, temp_pos_y2;
reg pos_x, pos_y;
reg [DATA_WIDTH-1:0] red, blue, green;
reg [DATA_WIDTH-1:0] red_cache[4], blue_cache[4], green_cache[4];
reg [1:0] raw_type;
integer i;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= 0;
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= 0;
if(reset) begin
for(i=0;i<4;i=i+1) red_cache[i] <= 0;
for(i=0;i<4;i=i+1) blue_cache[i] <= 0;
for(i=0;i<4;i=i+1) green_cache[i] <= 0;
pipeline_valid <= 0;
{red, green, blue} <= 0;
{out_data[2], out_data[1], out_data[0]} <= 0;
{out_hsync, out_fsync} <= 0;
pos_x <= ~0;
pos_y <= ~0;
temp_pos_x1 <= ~0;
temp_pos_y1 <= ~0;
temp_pos_x2 <= ~0;
temp_pos_y2 <= ~0;
raw_type <= RAW_TYPE;
end else if (pipeline_running) begin
{out_data[2],out_data[1],out_data[0]} <= 0;
for(i=0;i<PIPILINE;i=i+1) pipeline_user[i] <= 0;
pos_x <= 0;
pos_y <= 0;
end else if(pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if (in_valid) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache0[i] <= in_data[i];
pos_x <= (pos_x >= TOTAL_WIDTH - 1) ? (0) : (pos_x + 1);
pos_y <= (pos_x >= TOTAL_WIDTH - 1)?((pos_y >= TOTAL_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
if(in_valid) begin
pipeline_user[0] <= in_user;
pos_x <= (in_user[0])?(0):(~pos_x);
pos_y <= (in_user[0])?((in_user[1])?(0):(~pos_y)):(pos_y);
red_cache[0] <= (in_data[3] >> 1) + (in_data[5] >> 1);
red_cache[1] <= (in_data[0] >> 2) + (in_data[2] >> 2) + (in_data[6] >> 2) + (in_data[8] >> 2);
red_cache[2] <= in_data[4];
red_cache[3] <= (in_data[1] >> 1) + (in_data[7] >> 1);
green_cache[0] <= in_data[4];
green_cache[1] <= (in_data[1] >> 2) + (in_data[3] >> 2) + (in_data[5] >> 2) + (in_data[7] >> 2);
green_cache[2] <= (in_data[1] >> 2) + (in_data[3] >> 2) + (in_data[5] >> 2) + (in_data[7] >> 2);
green_cache[3] <= in_data[4];
blue_cache[0] <= (in_data[1] >> 1) + (in_data[7] >> 1);
blue_cache[1] <= in_data[4];
blue_cache[2] <= (in_data[0] >> 2) + (in_data[2] >> 2) + (in_data[6] >> 2) + (in_data[8] >> 2);
blue_cache[3] <= (in_data[3] >> 1) + (in_data[5] >> 1);
end
if (pipeline_valid[0]) begin
for (i = 0; i < DATA_NUM; i = i + 1) data_cache[i] <= data_cache0[i];
temp_pos_x1 <= pos_x;
temp_pos_y1 <= pos_y;
case (RAW_TYPE)
2'b00: raw_type <= {pos_y[0], pos_x[0]};
2'b01: raw_type <= {pos_y[0], ~pos_x[0]};
2'b10: raw_type <= {~pos_y[0], pos_x[0]};
2'b11: raw_type <= {~pos_y[0], ~pos_x[0]};
endcase
if(pipeline_valid[0]) begin
pipeline_user[1] <= pipeline_user[0];
out_data[2] <= red_cache[raw_type];
out_data[1] <= green_cache[raw_type];
out_data[0] <= blue_cache[raw_type];
end
if (pipeline_valid[1]) begin
temp_pos_x2 <= temp_pos_x1;
temp_pos_y2 <= temp_pos_y1;
case (raw_type)
0: begin // Missing B, R on G
blue <= (data_cache[1] >> 1) + (data_cache[7] >> 1);
red <= (data_cache[3] >> 1) + (data_cache[5] >> 1);
green <= data_cache[4];
end
1: begin // Missing G, R on B
green <= (data_cache[1] >> 2) + (data_cache[3] >> 2) + (data_cache[5] >> 2) + (data_cache[7] >> 2);
red <= (data_cache[0] >> 2) + (data_cache[2] >> 2) + (data_cache[6] >> 2) + (data_cache[8] >> 2);
blue <= data_cache[4];
end
2: begin // Missing G, B on R
green <= (data_cache[1] >> 2) + (data_cache[3] >> 2) + (data_cache[5] >> 2) + (data_cache[7] >> 2);
blue <= (data_cache[0] >> 2) + (data_cache[2] >> 2) + (data_cache[6] >> 2) + (data_cache[8] >> 2);
red <= data_cache[4];
end
3: begin // Missing B, R on G
red <= (data_cache[1] >> 1) + (data_cache[7] >> 1);
blue <= (data_cache[3] >> 1) + (data_cache[5] >> 1);
green <= data_cache[4];
end
endcase
end
if (pipeline_valid[2]) begin
{out_data[2], out_data[1], out_data[0]} <= {red, green, blue};
out_hsync <= (temp_pos_x2 == 0);
out_fsync <= ((temp_pos_x2 == 0) && (temp_pos_y2 == 0));
end
end
end
// 0:grg 1:rgr 2:bgb 3:gbg 036 窗口右移，0<->1 2<->3; 窗口下移，0<->2，1<->3。
// bgb gbg grg rgr 147
// grg rgr bgb gbg 258
always @(*) begin
case (RAW_TYPE)
2'b00: raw_type = { pos_y, pos_x};
2'b01: raw_type = { pos_y, ~pos_x};
2'b10: raw_type = {~pos_y, pos_x};
2'b11: raw_type = {~pos_y, ~pos_x};
endcase
end
endmodule

1
rtl/BayerProcess/Gowin_SDPB.sv
View File

@@ -1,5 +1,4 @@
//Gowin SDPB IP<49>˷<EFBFBD><CBB7><EFBFBD><EFBFBD>ļ<EFBFBD>
`timescale 1ns / 1ps
module Gowin_SDPB (
input wire clka,
input wire clkb, //no use

122
rtl/BayerProcess/SHIFT_REGISTER.sv
View File

@@ -1,72 +1,102 @@
//RAM-BASED移位寄存器
`timescale 1ns / 1ps
module SHIFT_REGISTER #(
parameter reg [4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
parameter IMAGE_WIDTH = 1936, //MAX 2048
parameter IFOUTIMME = 1'b0 //此项为0时，直至RAM存满IMAGE_WIDTH后再输出valid，为1时立即输出valid，无论是否存满
) (
parameter reg [ 4:0] DATA_WIDTH = 16, // 输入/输出数据位宽
parameter IFOUTIMME = 1'b0 //此项为0时，直至RAM存满IMAGE_WIDTH后再输出valid，为1时立即输出valid，无论是否存满
)(
// 基本信号
input wire clk,
input wire reset,
// 数据线
input wire [DATA_WIDTH - 1:0] in_data,
input wire [7:0] in_user, //in_user[0]是hstart, 行开始标志位, 用于给SHIFT_REGISTER判断输出与输入data的addr距离
output wire [DATA_WIDTH - 1:0] out_data,
output wire [7:0] out_user,
// 有效信号
input wire in_valid, // 上一模块输出数据有效
output wire out_valid // 当前模块输出数据有效
input wire in_valid, // 上一模块输出数据有效
output wire out_valid // 当前模块输出数据有效
);
reg [10:0] addr_a, addr_b;
wire cea, ceb;
reg fulldone;
reg [10:0] addr_a, addr_b;
wire cea, ceb;
reg fulldone;
reg in_valid_temp0, in_valid_temp1;
always @(posedge clk) in_valid_temp0 <= in_valid && (fulldone || IFOUTIMME);
always @(posedge clk) in_valid_temp1 <= in_valid_temp0;
reg in_valid_temp0, in_valid_temp1;
always @(posedge clk) in_valid_temp0 <= in_valid && (fulldone || IFOUTIMME);
always @(posedge clk) in_valid_temp1 <= in_valid_temp0;
assign cea = in_valid;
assign ceb = in_valid_temp0;
assign out_valid = in_valid_temp1;
assign cea = in_valid;
assign ceb = in_valid_temp0;
assign out_valid = in_valid_temp1;
always @(posedge clk) begin
if (reset) fulldone <= 0;
else if (addr_b == IMAGE_WIDTH - 1) fulldone <= 1;
else fulldone <= fulldone;
end
always @(posedge clk) begin
if (reset) begin
addr_a <= IMAGE_WIDTH + 1;
addr_b <= 0;
end else if (cea) begin
addr_a <= addr_a + 1;
addr_b <= addr_b + 1;
wire hstart;
assign hstart = in_user[0];
reg [15:0] wr_rd_distance_cnt;
always @(posedge clk) begin
if(reset) begin
addr_a <= ~0;
addr_b <= 0;
wr_rd_distance_cnt <= 0;
end else if(cea) begin
addr_a <= addr_a + 1;
if(hstart) begin
wr_rd_distance_cnt <= 0;
addr_b <= addr_a + 1 - (wr_rd_distance_cnt + 2);
end else begin
addr_a <= addr_a;
addr_b <= addr_b;
addr_b <= addr_b + 1;
wr_rd_distance_cnt <= wr_rd_distance_cnt + 1;
end
end else begin
addr_a <= addr_a;
addr_b <= addr_b;
wr_rd_distance_cnt <= wr_rd_distance_cnt;
end
end
// Single-Double-Port-BRAM-IP Bypass Normal
Gowin_SDPB Gowin_SDPB_inst (
.clka (clk), //input clka
.clkb (clk), //input clkb
.reset(reset), //input reset
always @(posedge clk) begin
if(reset) fulldone <= 0;
else if(cea && hstart && (addr_b != 0)) fulldone <= 1;
else fulldone <= fulldone;
end
.cea(cea), //input cea
.ceb(ceb), //input ceb
wire [15:0] din, dout;
assign din = {{(16-DATA_WIDTH){1'b0}},in_data};
assign out_data = dout[DATA_WIDTH-1:0];
// Single-Double-Port-BRAM-IP Bypass Normal
Gowin_SDPB Gowin_SDPB_inst(
.clka(clk), //input clka
.clkb(clk), //input clkb
.reset(reset), //input reset
.ada(addr_a), //input [10:0] ada
.adb(addr_b), //input [10:0] adb
.cea(cea), //input cea
.ceb(ceb), //input ceb
.din (in_data), //input [15:0] din
.dout(out_data), //output [15:0] dout
.ada(addr_a), //input [10:0] ada
.adb(addr_b), //input [10:0] adb
.oce(1) //input oce
);
.din(din), //input [15:0] din
.dout(dout), //output [15:0] dout
.oce(1) //input oce
);
// Single-Double-Port-BRAM-IP Bypass Normal
Gowin_SDPB_USER Gowin_SDPB_user_inst(
.clka(clk), //input clka
.clkb(clk), //input clkb
.reset(reset), //input reset
.cea(cea), //input cea
.ceb(ceb), //input ceb
.ada(addr_a), //input [10:0] ada
.adb(addr_b), //input [10:0] adb
.din(in_user), //input [7:0] din
.dout(out_user), //output [7:0] dout
.oce(1) //input oce
);
endmodule

203
rtl/BayerProcess/Windows.sv
View File

@@ -1,36 +1,41 @@
`timescale 1ns / 1ps
module Windows #(
parameter DATA_WIDTH = 16,
parameter IMAGE_WIDTH = 1936,
parameter IMAGE_HEIGHT = 1088,
parameter WINDOWS_WIDTH = 3,
parameter WINDOWS_ANCHOR_X = 1, //禁止大于WINDOWS_WIDTH-1
parameter WINDOWS_ANCHOR_Y = 1 //禁止大于WINDOWS_WIDTH-1
) (
// 基本信号
parameter DATA_WIDTH = 16,
parameter WINDOWS_WIDTH = 3,
parameter WINDOWS_ANCHOR_X = 1,//<2F><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>WINDOWS_WIDTH-1
parameter WINDOWS_ANCHOR_Y = 1 //<2F><>ֹ<EFBFBD><D6B9><EFBFBD><EFBFBD>WINDOWS_WIDTH-1
)(
// <20><><EFBFBD><EFBFBD><EFBFBD>ź<EFBFBD>
input wire clk,
input wire reset,
// 数据线
// <EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
input wire [DATA_WIDTH - 1:0] in_data,
output reg [DATA_WIDTH - 1:0] out_data[WINDOWS_WIDTH*WINDOWS_WIDTH], // 数据输出线
// 有效信号
input wire in_valid, // 上一模块输出数据有效
output reg out_valid, // 当前模块输出数据有效
// 准备信号 Windows模块无法停止，因此默认不处理准备信号
input wire [7:0] in_user,
output reg [DATA_WIDTH - 1:0] out_data [WINDOWS_WIDTH*WINDOWS_WIDTH], // <20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
output wire [7:0] out_user,
// <20><>Ч<EFBFBD>ź<EFBFBD>
input wire in_valid, // <20><>һģ<D2BB><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
output wire out_valid, // <20><>ǰģ<C7B0><C4A3><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ч
// ׼<><D7BC><EFBFBD>ź<EFBFBD> Windowsģ<73><C4A3><EFBFBD>޷<EFBFBD>ֹͣ<CDA3><D6B9><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ĭ<EFBFBD>ϲ<EFBFBD><CFB2><EFBFBD><EFBFBD><EFBFBD>׼<EFBFBD><D7BC><EFBFBD>ź<EFBFBD>
input wire in_ready,
output wire out_ready
);
assign out_ready = 1'b1;
assign out_ready = 1'b1;
reg [DATA_WIDTH - 1:0] regx_in_data [WINDOWS_WIDTH-1];
reg [DATA_WIDTH - 1:0] regx_out_data[WINDOWS_WIDTH-1];
reg [WINDOWS_WIDTH - 2:0] regx_in_valid, regx_out_valid;
reg [DATA_WIDTH - 1:0] regx_in_data[WINDOWS_WIDTH-1];
wire [DATA_WIDTH - 1:0] regx_out_data[WINDOWS_WIDTH-1];
reg [7:0] regx_in_user[WINDOWS_WIDTH-1];
wire [7:0] regx_out_user[WINDOWS_WIDTH-1];
reg [WINDOWS_WIDTH - 2:0] regx_in_valid;
wire [WINDOWS_WIDTH - 2:0] regx_out_valid;
reg [DATA_WIDTH - 1:0] data_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)];
reg [DATA_WIDTH - 1:0] data_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)];
reg [7:0] user_out_shift[WINDOWS_WIDTH-1][2*(WINDOWS_WIDTH-1)];
reg [7:0] out_user_windows[WINDOWS_WIDTH*WINDOWS_WIDTH];
assign out_user = out_user_windows[(WINDOWS_WIDTH*WINDOWS_ANCHOR_Y) + WINDOWS_ANCHOR_X];
/* outdata[x]:
/* outdata[x]:
SHIFT_REG1 -> 0 3 6 . .
SHIFT_REG0 -> 1 4 7 . .
in_data -> 2 5 8 . .
@@ -38,88 +43,98 @@ SHIFT_REG0 -> 1 4 7 . .
. . .
*/
reg firstframedone;
reg [15:0] pos_x, pos_y;
always @(posedge clk) begin
if (reset) begin
pos_x <= 0;
pos_y <= 0;
firstframedone <= 0;
end else if (regx_out_valid[WINDOWS_WIDTH-2]) begin
pos_x <= (pos_x >= IMAGE_WIDTH - 1) ? (0) : (pos_x + 1);
pos_y <= (pos_x >= IMAGE_WIDTH - 1)?((pos_y >= IMAGE_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
firstframedone <= (pos_x >= IMAGE_WIDTH - 1 && pos_y >= IMAGE_HEIGHT - 1)?(1):(firstframedone);
end else begin
pos_x <= pos_x;
pos_y <= pos_y;
firstframedone <= firstframedone;
end
end
reg out_valid_output;
reg firstframedone;
always @(posedge clk) begin
if(reset) firstframedone <= 0;
else if(out_user == 1'b1) firstframedone <= 1;
else firstframedone <= firstframedone;
end
always @(posedge clk) begin
if(reset) out_valid_output <= 0;
else out_valid_output <= regx_out_valid[WINDOWS_WIDTH-2];
end
assign out_valid = out_valid_output & (firstframedone || out_user);
integer i, j;
always @(posedge clk) begin
if (reset) begin
for (i = 0; i < WINDOWS_WIDTH * WINDOWS_WIDTH; i = i + 1) out_data[i] <= 0;
out_valid <= 0;
end else if (regx_out_valid[WINDOWS_WIDTH-2]) begin
for (i = 0; i < WINDOWS_WIDTH; i = i + 1) begin
for (j = 0; j < WINDOWS_WIDTH; j = j + 1) begin
if (i == WINDOWS_WIDTH - 1) begin
if (j == 0) out_data[(WINDOWS_WIDTH*i)+j] <= regx_out_data[WINDOWS_WIDTH-2];
else out_data[(WINDOWS_WIDTH*i)+j] <= data_out_shift[j-1][2*j-1];
end else out_data[(WINDOWS_WIDTH*i)+j] <= out_data[(WINDOWS_WIDTH*(i+1))+j];
integer i,j;
always @(posedge clk) begin
if(reset)begin
for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH;i=i+1) out_data[i] <= 0;
for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH;i=i+1) out_user_windows[i] <= 0;
end else if(regx_out_valid[WINDOWS_WIDTH-2])begin
for(i=0;i<WINDOWS_WIDTH;i=i+1) begin
for(j=0;j<WINDOWS_WIDTH;j=j+1) begin
if(i==WINDOWS_WIDTH-1) begin
if(j==0) out_data[(WINDOWS_WIDTH*i)+j] <= regx_out_data[WINDOWS_WIDTH-2];
else out_data[(WINDOWS_WIDTH*i)+j] <= data_out_shift[j-1][2*j-1];
end
else out_data[(WINDOWS_WIDTH*i)+j] <= out_data[(WINDOWS_WIDTH*(i+1))+j];
end
end
end
if (firstframedone) out_valid <= 1;
else
out_valid <= ~((pos_y <= WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1 && pos_x < WINDOWS_WIDTH-WINDOWS_ANCHOR_X-1) || (pos_y < WINDOWS_WIDTH-WINDOWS_ANCHOR_Y-1));
end else begin
for (i = 0; i < WINDOWS_WIDTH * WINDOWS_WIDTH - 1; i = i + 1) out_data[i] <= out_data[i];
out_valid <= 0;
end
end
always @(posedge clk) begin
if (reset)
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1)
for (j = 0; j < WINDOWS_WIDTH - 1; j = j + 1) data_out_shift[i][j] <= 0;
else
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
for (j = 0; j < 2 * (WINDOWS_WIDTH - 1); j = j + 1) begin
if (i == WINDOWS_WIDTH - 2 && j == 0) data_out_shift[i][j] <= in_data;
else if (j == 0) data_out_shift[i][j] <= regx_out_data[(WINDOWS_WIDTH-2-i)-1];
else data_out_shift[i][j] <= data_out_shift[i][j-1];
for(i=0;i<WINDOWS_WIDTH;i=i+1) begin
for(j=0;j<WINDOWS_WIDTH;j=j+1) begin
if(i==WINDOWS_WIDTH-1) begin
if(j==0) out_user_windows[(WINDOWS_WIDTH*i)+j] <= regx_out_user[WINDOWS_WIDTH-2];
else out_user_windows[(WINDOWS_WIDTH*i)+j] <= user_out_shift[j-1][2*j-1];
end
else out_user_windows[(WINDOWS_WIDTH*i)+j] <= out_user_windows[(WINDOWS_WIDTH*(i+1))+j];
end
end
end
end
always @(*) begin
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
if (i == 0) regx_in_data[i] = in_data;
else regx_in_data[i] = regx_out_data[i-1];
end else begin
for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH-1;i=i+1) out_data[i] <= out_data[i];
for(i=0;i<WINDOWS_WIDTH*WINDOWS_WIDTH-1;i=i+1) out_user_windows[i] <= out_user_windows[i];
end
for (i = 0; i < WINDOWS_WIDTH - 1; i = i + 1) begin
if (i == 0) regx_in_valid[i] = in_valid;
else regx_in_valid[i] = regx_out_valid[i-1];
end
end
end
generate
genvar o;
for (o = 0; o < WINDOWS_WIDTH - 1; o = o + 1'b1) begin : shift_register
SHIFT_REGISTER #(
.DATA_WIDTH (DATA_WIDTH),
.IMAGE_WIDTH(IMAGE_WIDTH),
.IFOUTIMME (1'b1)
) shift_registerx (
always @(posedge clk) begin
if(reset) for(i=0;i<WINDOWS_WIDTH-1;i=i+1) for(j=0;j<WINDOWS_WIDTH-1;j=j+1) begin
data_out_shift[i][j] <= 0;
user_out_shift[i][j] <= 0;
end else for(i=0;i<WINDOWS_WIDTH-1;i=i+1) begin
for(j=0;j<2*(WINDOWS_WIDTH-1);j=j+1) begin
if(i==WINDOWS_WIDTH-2 && j==0) data_out_shift[i][j] <= in_data;
else if(j==0) data_out_shift[i][j] <= regx_out_data[(WINDOWS_WIDTH-2-i)-1];
else data_out_shift[i][j] <= data_out_shift[i][j-1];
if(i==WINDOWS_WIDTH-2 && j==0) user_out_shift[i][j] <= in_user;
else if(j==0) user_out_shift[i][j] <= regx_out_user[(WINDOWS_WIDTH-2-i)-1];
else user_out_shift[i][j] <= user_out_shift[i][j-1];
end
end
end
always @(*) begin
for(i=0;i<WINDOWS_WIDTH-1;i=i+1)begin
if(i == 0) regx_in_data[i] = in_data;
else regx_in_data[i] = regx_out_data[i-1];
end
for(i=0;i<WINDOWS_WIDTH-1;i=i+1)begin
if(i == 0) regx_in_user[i] = in_user;
else regx_in_user[i] = regx_out_user[i-1];
end
for(i=0;i<WINDOWS_WIDTH-1;i=i+1)begin
if(i == 0) regx_in_valid[i] = in_valid;
else regx_in_valid[i] = regx_out_valid[i-1];
end
end
generate
genvar o;
for(o = 0; o < WINDOWS_WIDTH - 1; o = o + 1'b1) begin:shift_register
SHIFT_REGISTER #(
.DATA_WIDTH(DATA_WIDTH),
.IFOUTIMME(1'b1)
)shift_registerx(
.clk (clk),
.reset (reset),
.in_data (regx_in_data[o]),
.in_user (regx_in_user[o]),
.out_data (regx_out_data[o]),
.out_user (regx_out_user[o]),
.in_valid (regx_in_valid[o]),
.out_valid(regx_out_valid[o])
);
end
endgenerate
);
end
endgenerate
endmodule
endmodule

86
rtl/BayerProcess/Windows_tb.sv Normal file
View File

@@ -0,0 +1,86 @@
`default_nettype none
module Windows_tb ();
// Related Paras
parameter int CLK_PERIOD = 20;
parameter int DATA_WIDTH = 16;
parameter int WINDOWS_WIDTH = 5;
parameter int DATA_LENGTH = 100;
parameter int DATA_HEIGHT = 100;
parameter int DATA_FLAMES = 3;
// Related Ports
bit clk = 1;
bit rst = 0;
logic in_valid = 0;
logic [DATA_WIDTH - 1:0] in_data = 0;
logic [7:0] in_user = 0;
logic out_valid = 0;
logic [DATA_WIDTH - 1:0] out_data[WINDOWS_WIDTH ** 2] = '{default: 0};
logic [7:0] out_user = 0;
logic in_ready = 0;
logic out_ready = 0;
// Generate Clk
always #(CLK_PERIOD / 2) clk = ~clk;
// Reset Module
initial begin
rst = 1;
#(10 * CLK_PERIOD);
rst = 0;
end
// Send Data
initial begin
#(12 * CLK_PERIOD);
in_ready = 1;
#(3 * CLK_PERIOD);
for (int f = 0; f < DATA_FLAMES; ++f) begin
for (int j = 0; j < DATA_HEIGHT; ++j) begin
for (int i = 0; i < DATA_LENGTH; ++i) begin
in_user[1] = (j == 0 && i == 0) ? 1'b1 : 1'b0;
in_user[0] = (i == 0) ? 1'b1 : 1'b0;
in_data = j * DATA_LENGTH + i;
in_valid = 1;
#CLK_PERIOD;
end
end
in_valid = 0;
in_user = 0;
#(50 * CLK_PERIOD);
end
$finish(100 * CLK_PERIOD);
end
// Connect to modules
GSR GSR (.GSRI(1'b1));
Windows #(
.DATA_WIDTH (DATA_WIDTH),
.WINDOWS_WIDTH (WINDOWS_WIDTH),
.WINDOWS_ANCHOR_X(2),
.WINDOWS_ANCHOR_Y(2)
) Windows_inst (
.clk (clk),
.reset(rst),
.in_valid(in_valid),
.in_data (in_data),
.in_user (in_user),
.out_valid(out_valid),
.out_data (out_data),
.out_user (out_user),
.in_ready (in_ready),
.out_ready(out_ready)
);
endmodule

121
rtl/BayerProcess/fifo_isp_adapter.sv Normal file
View File

@@ -0,0 +1,121 @@
module fifo_isp_adapter #(
parameter DATA_WIDTH = 16
) (
input wire reset,
input wire camera_clk,
input wire in_valid,
input wire [DATA_WIDTH - 1:0] in_data,
input wire in_fsync,
input wire in_hsync,
input wire isp_clk,
output reg out_valid,
output reg [DATA_WIDTH - 1:0] out_data,
output reg [7:0] out_user
);
localparam GIVEUP_FRAME = 1;
reg [5:0] frame_count;
wire flag_frame_init_done;
// assign flag_frame_init_done = (frame_count >= GIVEUP_FRAME);
assign flag_frame_init_done = 1;
reg in_valid_d0, in_fsync_d0, in_hsync_d0;
wire in_fsync_pos, in_hsync_pos;
assign in_fsync_pos = in_fsync && !in_fsync_d0;
assign in_hsync_pos = in_hsync && !in_hsync_d0;
always @(posedge camera_clk) begin
if (reset) in_fsync_d0 <= 0;
else in_fsync_d0 <= in_fsync;
end
always @(posedge camera_clk) begin
if (reset) in_hsync_d0 <= 0;
else in_hsync_d0 <= in_hsync;
end
always @(posedge camera_clk) begin
if (reset) frame_count <= 0;
else if (in_fsync_pos && frame_count <= GIVEUP_FRAME - 1) frame_count <= frame_count + 1;
else frame_count <= frame_count;
end
reg fstart, hstart;
reg fifo_in_valid;
reg [DATA_WIDTH-1:0] in_data_d0;
reg [23:0] fifo_in_data;
always @(posedge camera_clk) begin
if (reset) begin
hstart <= 0;
fstart <= 0;
fifo_in_valid <= 0;
fifo_in_data <= 0;
in_valid_d0 <= 0;
in_data_d0 <= 0;
end else begin
if (in_valid) in_data_d0 <= in_data;
else in_data_d0 <= in_data_d0;
in_valid_d0 <= in_valid;
if (in_fsync_pos) fstart <= 1;
else if (in_valid_d0 && flag_frame_init_done) fstart <= 0;
else fstart <= fstart;
if (in_hsync_pos) hstart <= 1;
else if (in_valid_d0 && flag_frame_init_done) hstart <= 0;
else hstart <= hstart;
if (in_valid_d0 && flag_frame_init_done) begin
fifo_in_valid <= 1;
fifo_in_data <= {{(24 - 1 - 1 - DATA_WIDTH) {1'b0}}, fstart, hstart, in_data_d0};
end else begin
fifo_in_valid <= 0;
fifo_in_data <= fifo_in_data;
end
end
end
reg fifo_rd_en;
wire real_fifo_rd_en;
wire fifo_empty;
wire [23:0] fifo_out_data;
assign real_fifo_rd_en = fifo_rd_en & (~fifo_empty);
always @(posedge isp_clk) begin
if (reset) fifo_rd_en <= 0;
else if (~fifo_empty) fifo_rd_en <= 1;
else fifo_rd_en <= 0;
end
always @(posedge isp_clk) begin
if (reset) begin
out_valid <= 0;
out_user <= 0;
out_data <= 0;
end else if (real_fifo_rd_en) begin
out_valid <= 1;
out_data <= fifo_out_data[DATA_WIDTH-1:0];
out_user <= {6'b0, fifo_out_data[DATA_WIDTH+1], fifo_out_data[DATA_WIDTH]};
end else begin
out_valid <= 0;
out_data <= out_data;
end
end
Camera2ISP_fifo Camera2ISP_fifo_u (
.Data(fifo_in_data), //input [23:0] Data
.Reset(reset),
.WrClk(camera_clk), //input WrClk
.RdClk(isp_clk), //input RdClk
.WrEn(fifo_in_valid), //input WrEn
.RdEn(real_fifo_rd_en), //input RdEn
.Q(fifo_out_data), //output [23:0] Q
.Empty(fifo_empty), //output Empty
.Full() //output Full
);
endmodule

51
rtl/BayerProcess/frame_size_detect.sv Normal file
View File

@@ -0,0 +1,51 @@
module frame_size_detect (
input wire clk,
input wire reset,
input wire in_valid,
input wire hstart,
input wire fstart,
input wire [15:0] h_pixel,
input wire [15:0] v_pixel,
output wire h_pixel_correct,
output wire v_pixel_correct
);
reg [15:0] h_pixel_cnt, v_pixel_cnt;
reg [3:0] h_pixel_match_times, v_pixel_match_times;
assign h_pixel_correct = (h_pixel_match_times == 4'hF);
assign v_pixel_correct = (v_pixel_match_times == 4'hF);
always @(posedge clk) begin
if(reset) h_pixel_cnt <= 0;
else if(hstart & in_valid) h_pixel_cnt <= 0;
else if(in_valid) h_pixel_cnt <= h_pixel_cnt + 1;
else h_pixel_cnt <= h_pixel_cnt;
end
always @(posedge clk) begin
if(reset) h_pixel_match_times <= 0;
else if(hstart&in_valid) begin
if(h_pixel_cnt == h_pixel - 1) h_pixel_match_times <= (h_pixel_match_times == 4'hF)?(h_pixel_match_times):(h_pixel_match_times + 1);
else h_pixel_match_times <= 0;
end else h_pixel_match_times <= h_pixel_match_times;
end
always @(posedge clk) begin
if(reset) v_pixel_cnt <= 0;
else if(fstart & in_valid) v_pixel_cnt <= 0;
else if(hstart & in_valid) v_pixel_cnt <= v_pixel_cnt + 1;
else v_pixel_cnt <= v_pixel_cnt;
end
always @(posedge clk) begin
if(reset) v_pixel_match_times <= 0;
else if(fstart & in_valid) begin
if(v_pixel_cnt == v_pixel - 1) v_pixel_match_times <= (v_pixel_match_times == 4'hF)?(v_pixel_match_times):(v_pixel_match_times + 1);
else v_pixel_match_times <= 0;
end else v_pixel_match_times <= v_pixel_match_times;
end
endmodule