change simulate

FIFO/rptr_empty.v

@@ -37,7 +37,7 @@ module rptr_empty
 
     // Memory read-address pointer (okay to use binary to address memory)
     assign raddr     = rbin[ADDRSIZE-1:0];
-    assign rbinnext  = rbin + (rinc & ~rempty);
+    assign rbinnext  = rbin + {{(ADDRSIZE - 1){1'b0}},(rinc & ~rempty)};
     assign rgraynext = (rbinnext >> 1) ^ rbinnext;
     assign rgraynextm1 = ((rbinnext + 1'b1) >> 1) ^ (rbinnext + 1'b1);
 

FIFO/wptr_full.v

@@ -35,7 +35,7 @@ module wptr_full
 
     // Memory write-address pointer (okay to use binary to address memory)
     assign waddr = wbin[ADDRSIZE-1:0];
-    assign wbinnext  = wbin + (winc & ~wfull);
+    assign wbinnext  = wbin + {{(ADDRSIZE - 1){1'b0}}, (winc & ~wfull) };
     assign wgraynext = (wbinnext >> 1) ^ wbinnext;
     assign wgraynextp1 = ((wbinnext + 1'b1) >> 1) ^ (wbinnext + 1'b1);