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ISP
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Verilog 60.1%
C++ 25.7%
SystemVerilog 8.8%
Coq 4.8%
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SikongJueluo 21c763f54f
change simulate 		2024-05-15 21:54:11 +08:00
Crop finish isp testbench but still have some errors waiting to be deat with 2024-05-15 16:35:17 +08:00
Demosaic change simulate 2024-05-15 21:54:11 +08:00
FIFO change simulate 2024-05-15 21:54:11 +08:00
Merge change simulate 2024-05-15 21:54:11 +08:00
RAM finish isp testbench but still have some errors waiting to be deat with 2024-05-15 16:35:17 +08:00
Scaler update scaler and RAM 2024-05-11 21:53:35 +08:00
sim change simulate 2024-05-15 21:54:11 +08:00
.gitignore finish domosaic2 simulate 2024-05-14 21:00:19 +08:00
isp.v change simulate 2024-05-15 21:54:11 +08:00