66 lines
1.9 KiB
Verilog
66 lines
1.9 KiB
Verilog
// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module wptr_full
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#(
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parameter ADDRSIZE = 4
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)(
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input wire wclk,
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input wire wrst_n,
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input wire winc,
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input wire [ADDRSIZE :0] wq2_rptr,
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output reg wfull,
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output reg awfull,
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output wire [ADDRSIZE-1:0] waddr,
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output reg [ADDRSIZE :0] wptr
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);
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reg [ADDRSIZE:0] wbin;
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wire [ADDRSIZE:0] wgraynext, wbinnext, wgraynextp1;
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wire awfull_val, wfull_val;
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// GRAYSTYLE2 pointer
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always @(posedge wclk or negedge wrst_n) begin
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if (!wrst_n)
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{wbin, wptr} <= 0;
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else
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{wbin, wptr} <= {wbinnext, wgraynext};
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end
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// Memory write-address pointer (okay to use binary to address memory)
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assign waddr = wbin[ADDRSIZE-1:0];
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assign wbinnext = wbin + {{(ADDRSIZE - 1){1'b0}}, (winc & ~wfull) };
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assign wgraynext = (wbinnext >> 1) ^ wbinnext;
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assign wgraynextp1 = ((wbinnext + 1'b1) >> 1) ^ (wbinnext + 1'b1);
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//------------------------------------------------------------------
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// Simplified version of the three necessary full-tests:
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// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
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// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
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// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
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//------------------------------------------------------------------
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assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
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assign awfull_val = (wgraynextp1 == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
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always @(posedge wclk or negedge wrst_n) begin
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if (!wrst_n) begin
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awfull <= 1'b0;
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wfull <= 1'b0;
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end else begin
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awfull <= awfull_val;
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wfull <= wfull_val;
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end
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end
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endmodule
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`resetall
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