66 lines
1.8 KiB
Verilog
66 lines
1.8 KiB
Verilog
// distributed under the mit license
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// https://opensource.org/licenses/mit-license.php
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`timescale 1 ns / 1 ps
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`default_nettype none
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module rptr_empty
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#(
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parameter ADDRSIZE = 4
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)(
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input wire rclk,
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input wire rrst_n,
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input wire rinc,
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input wire [ADDRSIZE :0] rq2_wptr,
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output reg rempty,
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output reg arempty,
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output wire [ADDRSIZE-1:0] raddr,
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output reg [ADDRSIZE :0] rptr
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);
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reg [ADDRSIZE:0] rbin;
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wire [ADDRSIZE:0] rgraynext, rbinnext, rgraynextm1;
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wire arempty_val, rempty_val;
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//-------------------
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// GRAYSTYLE2 pointer
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//-------------------
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always @(posedge rclk or negedge rrst_n) begin
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if (!rrst_n)
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{rbin, rptr} <= 0;
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else
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{rbin, rptr} <= {rbinnext, rgraynext};
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end
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// Memory read-address pointer (okay to use binary to address memory)
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assign raddr = rbin[ADDRSIZE-1:0];
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assign rbinnext = rbin + {{(ADDRSIZE - 1){1'b0}},(rinc & ~rempty)};
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assign rgraynext = (rbinnext >> 1) ^ rbinnext;
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assign rgraynextm1 = ((rbinnext + 1'b1) >> 1) ^ (rbinnext + 1'b1);
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//---------------------------------------------------------------
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// FIFO empty when the next rptr == synchronized wptr or on reset
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//---------------------------------------------------------------
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assign rempty_val = (rgraynext == rq2_wptr);
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assign arempty_val = (rgraynextm1 == rq2_wptr);
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always @ (posedge rclk or negedge rrst_n) begin
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if (!rrst_n) begin
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arempty <= 1'b0;
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rempty <= 1'b1;
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end
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else begin
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arempty <= arempty_val;
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rempty <= rempty_val;
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end
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end
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endmodule
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`resetall
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