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SystemVerilog 62.7%
C++ 23.2%
Makefile 6.2%
Verilog 4.2%
Nix 2.2%
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SikongJueluo ee812630dd
add demosaic testbench using verilator 		2024-05-14 15:36:54 +08:00
Crop fix some bugs 2024-05-13 16:52:13 +08:00
Demosaic add demosaic testbench using verilator 2024-05-14 15:36:54 +08:00
FIFO first commit 2024-05-09 22:36:04 +08:00
Merge fix some bugs 2024-05-13 16:52:13 +08:00
RAM fix some bugs 2024-05-13 16:52:13 +08:00
Scaler update scaler and RAM 2024-05-11 21:53:35 +08:00
sim first commit 2024-05-09 22:36:04 +08:00
.gitignore fix some bugs 2024-05-13 16:52:13 +08:00
Makefile fix some bugs and pass lint check 2024-05-13 11:29:03 +08:00
isp.v fix some bugs 2024-05-13 16:52:13 +08:00
sc_main.cpp fix some bugs and pass lint check 2024-05-13 11:29:03 +08:00