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SikongJueluo d345fed4e7 finish sim

2024-05-16 21:39:15 +08:00

Crop

fix some errors

2024-05-16 17:33:39 +08:00

Demosaic

finish sim

2024-05-16 21:39:15 +08:00

FIFO

change fifo source and finish testbench file for isp

2024-05-16 17:15:25 +08:00

Merge

fix some errors

2024-05-16 17:33:39 +08:00

RAM

finish isp testbench but still have some errors waiting to be deat with

2024-05-15 16:35:17 +08:00

Scaler

update scaler and RAM

2024-05-11 21:53:35 +08:00

sim

finish sim

2024-05-16 21:39:15 +08:00

.gitignore

finish sim

2024-05-16 21:39:15 +08:00

isp.v

finish sim

2024-05-16 21:39:15 +08:00

Description

No description provided

9.6 MiB

Languages

Verilog 60.1%

C++ 25.7%

SystemVerilog 8.8%

Coq 4.8%

CMake 0.4%

Other 0.1%