finish sim

2024-05-16 21:39:15 +08:00
parent 5eebe6e922
commit d345fed4e7
10 changed files with 62 additions and 527 deletions
--- a/sim/Makefile
+++ b/sim/Makefile
@@ -44,6 +44,8 @@ VERILATOR_FLAGS += -Wall
 VERILATOR_FLAGS += --trace
 # Check SystemVerilog assertions
 VERILATOR_FLAGS += --assert
+# Enable multithreading
+# VERILATOR_FLAGS += --threads 4
 # Generate coverage analysis
 # VERILATOR_FLAGS += --coverage
 # Run Verilator in debug mode