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switch lsp to clangd and reconstruct project

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SikongJueluo
2024-09-15 22:04:48 +08:00
parent 61b91e0688
commit 7e12105a3d
47 changed files with 1931 additions and 2859 deletions
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99
rtl/Color/ColorBlender.sv Normal file
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`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module ColorBlender #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8 // 输出图像的色深
) (
input wire clk,
input wire reset,
input wire [16 - 1:0] in_data [3],
output reg [OUT_DEPTH - 1:0] out_data [3],
input wire in_valid,
output wire out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output wire out_hsync,
output wire out_fsync,
// 颜色校正
input wire [15:0] gain_red,
input wire [15:0] gain_green,
input wire [15:0] gain_blue,
input wire enable
);
localparam PIPELINE = 4;
reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid;
wire pipeline_flag;
assign pipeline_flag = (pipeline_valid[PIPELINE-1] == 0) | (in_ready);
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_flag;
//out_valid ：只要本模块有数据要发送就一直拉高
assign out_valid = pipeline_valid[PIPELINE-1];
assign out_hsync = pipeline_hsync[PIPELINE-1];
assign out_fsync = pipeline_fsync[PIPELINE-1];
reg [32 - 1:0] data_cal0[3];
reg [32 - 1:0] data_cal1[3];
reg [32 - 1:0] data_cal2[3];
integer i;
always @(posedge clk) begin
if(reset) begin
pipeline_valid <= 0;
pipeline_hsync <= 0;
pipeline_fsync <= 0;
for(i=0;i<3;i=i+1) data_cal0[i] <= 0;
for(i=0;i<3;i=i+1) data_cal1[i] <= 0;
for(i=0;i<3;i=i+1) data_cal2[i] <= 0;
for(i=0;i<3;i=i+1) out_data[i] <= 0;
end else if(pipeline_flag) begin
/************* 流水 ************/
pipeline_valid <= {pipeline_valid[PIPELINE-2:0], in_valid};
pipeline_hsync <= {pipeline_hsync[PIPELINE-2:0], in_hsync};
pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
/************* 1:计算1 ************/
if(in_valid) begin
data_cal0[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
data_cal0[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
end
/************* 2:计算2 ************/
if(pipeline_valid[0]) begin
if(enable) begin
data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
end else begin
data_cal1[0] <= data_cal0[0] >> 8;
data_cal1[1] <= data_cal0[1] >> 8;
data_cal1[2] <= data_cal0[2] >> 8;
end
end
/************* 3:计算3 ************/
if(pipeline_valid[1]) begin
data_cal2[0] <= (data_cal1[0][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[0];
data_cal2[1] <= (data_cal1[1][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[1];
data_cal2[2] <= (data_cal1[2][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[2];
end
/************* 4:发送结果 ************/
if(pipeline_valid[2]) begin
out_data[0] <= data_cal2[0][OUT_DEPTH-1:0];
out_data[1] <= data_cal2[1][OUT_DEPTH-1:0];
out_data[2] <= data_cal2[2][OUT_DEPTH-1:0];
end
end
end
endmodule

106
rtl/Color/GammaCorrection.sv Executable file
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`timescale 1ns / 1ps
module GammaCorrection #(
parameter reg [4:0] COLOR_DEPTH = 8
) (
input wire clk,
input wire reset,
input wire in_en,
input wire [COLOR_DEPTH - 1 : 0] in_data[3],
output wire out_ready,
output wire out_receive,
output reg out_en,
output reg [COLOR_DEPTH - 1 : 0] out_data[3],
input wire in_ready,
input wire in_receive,
input wire [7:0] gamma_table[256],
input wire enable
);
reg [2:0] state, nextState;
localparam reg [2:0] READ_DATA = 0;
localparam reg [2:0] SEND_DATA = 2;
reg [7:0] data_cache[3];
always @(posedge clk)
begin
if (reset)
state <= READ_DATA;
else
state <= nextState;
end
always @(*)
begin
case (state)
READ_DATA:
nextState = in_en ? SEND_DATA : READ_DATA;
SEND_DATA:
nextState = in_receive ? READ_DATA : SEND_DATA;
default:
nextState = READ_DATA;
endcase
end
assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
always @(posedge clk)
begin
if (reset)
begin
out_en <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
data_cache[0] <= 0;
data_cache[1] <= 0;
data_cache[2] <= 0;
end
else
begin
case (state)
READ_DATA:
begin
if (in_en)
begin
data_cache[0] <= in_data[0];
data_cache[1] <= in_data[1];
data_cache[2] <= in_data[2];
end
end
SEND_DATA:
begin
if (in_ready && !in_receive)
begin
out_en <= 1;
if (enable)
begin
out_data[0] <= gamma_table[data_cache[0]];
out_data[1] <= gamma_table[data_cache[1]];
out_data[2] <= gamma_table[data_cache[2]];
end
else
begin
out_data[0] <= data_cache[0];
out_data[1] <= data_cache[1];
out_data[2] <= data_cache[2];
end
end
else
out_en <= 0;
end
default:
;
endcase
end
end
endmodule

160
rtl/Color/GreyWorld.sv Executable file
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`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module GreyWorld #(
parameter reg [4:0] COLOR_DEPTH = 8,
parameter reg [31:0] IM_SIZE = 1920 * 1080
) (
input wire clk,
input wire reset,
input wire in_en,
input wire [7:0] in_data[3], // 0:R 1:G 2:B
output wire out_ready,
output wire out_receive,
// 输出相关
input wire in_ready,
input wire in_receive,
output reg out_en,
output reg [COLOR_DEPTH - 1:0] out_data[3],
// Gain: red = 0.803881, green = 0.885894, blue = 1.594308
input wire enable,
input wire [8:0] flame_rate,
input wire [15:0] white_gain[3]
);
reg [2:0] state, nextState, calState;
localparam reg [2:0] READ_DATA = 0;
localparam reg [2:0] CALC_DATA = 1;
localparam reg [2:0] SEND_DATA = 2;
reg [8:0] cnt_flame;
reg [31:0] red_total, green_total, blue_total;
reg [39:0] r_white_gain[3];
reg [31:0] data_cal[3], data_cache[3];
reg [31:0] cnt_pexels;
reg [39:0] average;
reg isCal;
always @(posedge clk) begin
if (reset) state <= READ_DATA;
else state <= nextState;
end
always @(*) begin
case (state)
READ_DATA: nextState = in_en ? CALC_DATA : READ_DATA;
CALC_DATA: nextState = isCal ? CALC_DATA : SEND_DATA;
SEND_DATA: nextState = in_receive ? READ_DATA : SEND_DATA;
default: nextState = READ_DATA;
endcase
end
assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
// assign average = (({8'b0, red_total } + {8'b0, green_total } + {8'b0, blue_total }) << 8) / 3 ;
// assign isCal = cnt_pexels >= IM_SIZE && cnt_flame == flame_rate;
always @(posedge clk) begin
if (reset) begin
red_total <= 0;
green_total <= 0;
blue_total <= 0;
cnt_flame <= flame_rate;
cnt_pexels <= 0;
calState <= 4;
r_white_gain[0] <= {24'b0, white_gain[0] };
r_white_gain[1] <= {24'b0, white_gain[1] };
r_white_gain[2] <= {24'b0, white_gain[2] };
data_cache[0] <= 0;
data_cache[1] <= 0;
data_cache[2] <= 0;
out_en <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
end else begin
case (state)
READ_DATA: begin
if (in_en) begin
data_cache[0] <= {24'b0, in_data[0]};
data_cache[1] <= {24'b0, in_data[1]};
data_cache[2] <= {24'b0, in_data[2]};
if (cnt_flame == flame_rate) begin
red_total <= red_total + {24'b0, in_data[0]};
green_total <= green_total + {24'b0, in_data[1]};
blue_total <= blue_total + {24'b0, in_data[2]};
end
if (cnt_pexels <= IM_SIZE) begin
cnt_pexels <= cnt_pexels + 1;
end else begin
cnt_pexels <= 0;
if (cnt_flame < flame_rate) cnt_flame <= cnt_flame + 1;
else cnt_flame <= 0;
if (cnt_pexels >= IM_SIZE && cnt_flame == flame_rate) isCal <= 1;
end
end
end
CALC_DATA: begin
if (calState == 0) begin
average <= {8'b0, red_total } + {8'b0, green_total };
calState <= 1;
end
else if (calState == 1) begin
average <= average + {8'b0, blue_total};
calState <= 2;
end
else if (calState == 2) begin
average <= average << 8;
calState <= 3;
end
else if (calState == 3) begin
r_white_gain[0] <= average / {8'b0, red_total};
r_white_gain[1] <= average / {8'b0, green_total};
r_white_gain[2] <= average / {8'b0, blue_total};
isCal <= 0;
calState <= 4;
end
else if (calState == 4) begin
data_cal[0] <= (data_cache[0] * r_white_gain[0][31:0]);
data_cal[1] <= (data_cache[1] * r_white_gain[1][31:0]);
data_cal[2] <= (data_cache[2] * r_white_gain[2][31:0]);
calState <= 5;
end
else begin
calState <= isCal ? 0 : 4;
end
end
SEND_DATA: begin
if (in_ready) begin
out_en <= 1;
if (enable) begin
out_data[0] <= (|data_cal[0][31:16]) ? 255 : (data_cal[0] > 0 ? data_cal[0][15:8] : 0);
out_data[1] <= (|data_cal[1][31:16]) ? 255 : (data_cal[1] > 0 ? data_cal[1][15:8] : 0);
out_data[2] <= (|data_cal[2][31:16]) ? 255 : (data_cal[2] > 0 ? data_cal[2][15:8] : 0);
end else begin
out_data[0] <= data_cache[0][7:0];
out_data[1] <= data_cache[1][7:0];
out_data[2] <= data_cache[2][7:0];
end
end else out_en <= 0;
end
default: ;
endcase
end
end
endmodule

163
rtl/Color/SaturationCorrection.sv Executable file
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`timescale 1ns / 1ps
module SaturationCorrection #(
parameter reg [4:0] COLOR_DEPTH = 8
) (
input wire clk,
input wire reset,
input wire in_en,
input wire [COLOR_DEPTH - 1 : 0] in_data[3],
output wire out_ready,
output wire out_receive,
output reg out_en,
output reg [COLOR_DEPTH - 1 : 0] out_data[3],
input wire in_ready,
input wire in_receive,
input wire enable,
input wire signed [31:0] saturation_inc
);
reg [2:0] state, nextState, calState;
localparam reg [2:0] READ_DATA = 0;
localparam reg [2:0] CALC_DATA = 1;
localparam reg [2:0] SEND_DATA = 2;
reg signed [31:0] data_cal[3], data_cache[3];
// wire signed [31:0] max, min, delta, value, light, saturation, alpha;
reg signed [31:0] max, min, delta, value, light, saturation, alpha;
always @(posedge clk) begin
if (reset) state <= READ_DATA;
else state <= nextState;
end
always @(*) begin
case (state)
READ_DATA: nextState = in_en ? 3 : READ_DATA;
3: nextState = CALC_DATA;
CALC_DATA: nextState = (calState >= 5 || !enable) ? SEND_DATA : CALC_DATA;
SEND_DATA: nextState = in_receive ? READ_DATA : SEND_DATA;
default: nextState = READ_DATA;
endcase
end
assign out_ready = (!in_en && state == READ_DATA && !reset) ? 1 : 0;
assign out_receive = (in_en && state == READ_DATA && !reset) ? 1 : 0;
// assign max = data_cache[0] > data_cache[1]?
// (data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]):
// (data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]);
// assign min = data_cache[0] < data_cache[1]?
// (data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]):
// (data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]);
// assign delta = max - min;
// assign value = max + min;
// assign light = value >>> 1;
// // // assign saturation = (light <= 128) ? (delta <<< 8) / value : (delta <<< 8) / (512 - value);
// assign saturation = (delta <<< 8) / max;
// assign alpha = (saturation_inc[31] == 0)
// ? ((saturation_inc + saturation >= 256)
// ? (65536 / saturation) - 256 : (65536 / (256 - saturation_inc)) - 256)
// : (saturation_inc);
always @(posedge clk) begin
if (reset) begin
calState <= 0;
out_en <= 0;
out_data[0] <= 0;
out_data[1] <= 0;
out_data[2] <= 0;
min <= 0;
max <= 0;
delta <= 0;
value <= 0;
light <= 0;
saturation <= 0;
alpha <= 0;
data_cal[0] <= 0;
data_cal[1] <= 0;
data_cal[2] <= 0;
data_cache[0] <= 0;
data_cache[1] <= 0;
data_cache[2] <= 0;
end else begin
case (state)
READ_DATA: begin
if (in_en) begin
data_cache[0] <= {24'b0, in_data[0]};
data_cache[1] <= {24'b0, in_data[1]};
data_cache[2] <= {24'b0, in_data[2]};
end
end
CALC_DATA: begin
if (enable) begin
if (calState == 0) begin
max <= data_cache[0] > data_cache[1]?
(data_cache[0] > data_cache[2] ? data_cache[0] : data_cache[2]):
(data_cache[1] > data_cache[2] ? data_cache[1] : data_cache[2]);
min <= data_cache[0] < data_cache[1]?
(data_cache[0] < data_cache[2] ? data_cache[0] : data_cache[2]):
(data_cache[1] < data_cache[2] ? data_cache[1] : data_cache[2]);
calState <= 1;
end else if (calState == 1) begin
delta <= max - min;
value <= max + min;
calState <= 2;
end else if (calState == 2) begin
light <= value >>> 1;
saturation <= (delta <<< 8) / max;
calState <= 3;
end else if (calState == 3) begin
alpha <= (saturation_inc[31] == 0) ? ((saturation_inc + saturation >= 255)
? (65536 / saturation) - 255 : (65536 / (256 - saturation_inc)) - 255)
: (saturation_inc);
calState <= 4;
end else if (calState == 4) begin
if (saturation_inc[31] == 0) begin
data_cal[0] <= (data_cache[0] << 8) + ((data_cache[0] - light) * alpha);
data_cal[1] <= (data_cache[1] << 8) + ((data_cache[1] - light) * alpha);
data_cal[2] <= (data_cache[2] << 8) + ((data_cache[2] - light) * alpha);
end else begin
data_cal[0] <= (light << 8) + (data_cache[0] - light) * (256 + alpha);
data_cal[1] <= (light << 8) + (data_cache[1] - light) * (256 + alpha);
data_cal[2] <= (light << 8) + (data_cache[2] - light) * (256 + alpha);
end
calState <= 5;
end else begin
calState <= 0;
end
end
end
SEND_DATA: begin
if (in_ready && !in_receive) begin
out_en <= 1;
if (enable && delta != 0) begin
out_data[0] <= (|data_cal[0][31:16]) ? 255 : (data_cal[0] > 0 ? data_cal[0][15:8] : 0);
out_data[1] <= (|data_cal[1][31:16]) ? 255 : (data_cal[1] > 0 ? data_cal[1][15:8] : 0);
out_data[2] <= (|data_cal[2][31:16]) ? 255 : (data_cal[2] > 0 ? data_cal[2][15:8] : 0);
end else begin
out_data[0] <= data_cache[0][7:0];
out_data[1] <= data_cache[1][7:0];
out_data[2] <= data_cache[2][7:0];
end
end else out_en <= 0;
end
default: ;
endcase
end
end
endmodule

135
rtl/Color/WhiteBalance.sv Executable file
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`timescale 1ns / 1ps
// 三通道图像合成一个RGB图像
module WhiteBalance #(
parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
parameter reg [4:0] OUT_DEPTH = 8, // 输出图像的色深
parameter reg [8:0] BUFF_SIZE = 32,
parameter reg [31:0] RAM_BEGIN_ADDR = 0,
parameter reg [31:0] IM_SIZE = 1920 * 1080
) (
input wire clk,
input wire reset,
input wire in_en,
input wire [15:0] in_data[3], // 0:R 1:G 2:B
output wire out_ready,
output wire out_receive,
// 输出相关
input wire in_ready,
input wire in_receive,
output wire out_en,
output wire [OUT_DEPTH - 1:0] out_data[3],
input wire enable,
input wire [8:0] flame_rate,
input wire [31:0] white_gain[3]
);
wire ram_read_en, ram_write_en, ram_read_ready, ram_write_ready;
wire [31:0] ram_read_data, ram_read_addr, ram_write_data, ram_write_addr;
reg [8:0] cnt_flame;
reg [31:0] cnt_in_pic, cnt_out_pic, cnt_pixels;
reg [31:0] red_total, green_total, blue_total;
reg [31:0] r_white_gain[3];
wire is_finish_cal;
always @(*) begin
if (cnt_in_pic >= IM_SIZE) is_finish_cal = 1;
else if (cnt_out_pic >= IM_SIZE) is_finish_cal = 0;
else is_finish_cal = is_finish_cal;
end
assign ram_read_addr = cnt_out_pic;
assign ram_write_addr = cnt_in_pic;
assign cnt_pixels = (is_finish_cal)
? IM_SIZE - cnt_out_pic + cnt_in_pic
: cnt_in_pic - cnt_out_pic;
assign out_ready = (!in_en && !reset && cnt_pixels < IM_SIZE) ? 1 : 0;
assign out_receive = (in_en && !reset && cnt_in_pic < IM_SIZE) ? 1 : 0;
DiffWidthSyncFIFO #(
.DATA_WIDTH (8),
.DATA_DEPTH (12),
.READ_DEPTH (4),
.WRITE_DEPTH(3)
) in_fifo (
.clk(clk),
.reset(reset),
.read_ready(ram_write_ready),
.read_en(ram_write_en),
.read_data(ram_write_data),
.write_ready(in_ready),
.write_en(in_en),
.write_data(in_data)
);
DiffWidthSyncFIFO #(
.DATA_WIDTH (8),
.DATA_DEPTH (12),
.READ_DEPTH (3),
.WRITE_DEPTH(4)
) out_fifo (
.clk(clk),
.reset(reset),
.read_ready(out_ready),
.read_en(out_en),
.read_data(out_data),
.write_ready(ram_read_ready),
.write_en(ram_read_en),
.write_data(ram_read_data)
);
SDRAM inst_RAM (
.clk(clk),
.read_en(ram_read_en),
.read_addr(ram_read_addr),
.read_data(ram_read_data),
.read_ready(ram_read_ready),
.write_en(ram_write_en),
.write_addr(ram_write_addr),
.write_data(ram_write_data),
.write_ready(ram_write_ready)
);
// calculate white gain
always @(posedge clk) begin
if (reset) begin
red_total <= 0;
green_total <= 0;
blue_total <= 0;
cnt_flame <= 0;
cnt_in_pic <= 0;
r_white_gain[0] <= white_gain[0];
r_white_gain[1] <= white_gain[1];
r_white_gain[2] <= white_gain[2];
end else begin
if (in_en && cnt_pixels < IM_SIZE) begin
red_total <= red_total + in_data[0];
green_total <= green_total + in_data[1];
blue_total <= blue_total + in_data[2];
if (cnt_in_pic < IM_SIZE) cnt_in_pic <= cnt_in_pic + 1;
else cnt_in_pic <= 0;
end else begin
end
end
end
// calculate out data
always @(posedge clk) begin
if (reset) begin
cnt_out_pic <= 0;
end else begin
if (out_ready && is_finish_cal) begin
out_en <= 1;
end else begin
out_en <= 0;
end
end
end
endmodule

106
rtl/Crop/Crop.sv Normal file
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`timescale 1ns / 1ps
module Crop #(
parameter IN_WIDTH = 512,
parameter IN_HEIGHT = 512,
parameter OFFSET_X = 120,
parameter OFFSET_Y = 256,
// parameter TRANSLAYT_X = 120,
// parameter TRANSLAYT_Y = 120,
parameter OUT_WIDTH = 512,
parameter OUT_HEIGHT = 512,
parameter BLANK_COLOR = 6'h000000,
parameter COLOR_DEPTH = 16
) (
input wire clk,
input wire reset,
input wire [COLOR_DEPTH - 1:0] in_data [3],
output reg [COLOR_DEPTH - 1:0] out_data[3],
input wire in_valid,
output reg out_valid,
input wire in_ready,
output wire out_ready,
input wire in_hsync,
input wire in_fsync,
output reg out_hsync,
output reg out_fsync
);
localparam PIPILINE = 3;
reg [PIPILINE-1:0] pipeline_valid;
wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
reg [31:0] cnt_x, cnt_y, temp_x, temp_y;
reg force_dis, force_en;
reg [COLOR_DEPTH-1:0] data_cache0[3];
reg [COLOR_DEPTH-1:0] data_cache1[3];
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = (pipeline_valid[PIPILINE-1] & ~force_dis) | force_en;
//分别表示当前像素: 显示；被裁掉；空。
reg [1:0] flag_crop;
localparam CROP_ERROR = 2'b00, CROP_KEEP = 2'b01, CROP_GIVE_UP = 2'b10, CROP_BLANK = 2'b11;
integer i;
always @(posedge clk) begin
if (reset) begin
pipeline_valid <= 0;
cnt_x <= 0;
cnt_y <= 0;
for (i = 0; i < 3; i++) data_cache0[i] <= 0;
for (i = 0; i < 3; i++) data_cache1[i] <= 0;
for (i = 0; i < 3; i++) out_data[i] <= 0;
flag_crop <= 0;
force_dis <= 0;
force_en <= 0;
out_hsync <= 0;
out_fsync <= 0;
temp_x <= 0;
temp_y <= 0;
end else if (pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if (in_valid) begin //when 00
for (i = 0; i < 3; i++) data_cache0[i] <= in_data[i];
cnt_x <= (in_hsync) ? (0) : (cnt_x + 1);
cnt_y <= (in_hsync) ? ((in_fsync) ? (0) : (cnt_y + 1)) : (cnt_y);
end
if (pipeline_valid[0]) begin //when 00
for (i = 0; i < 3; i++) data_cache1[i] <= data_cache0[i];
temp_x <= cnt_x;
temp_y <= cnt_y;
if (cnt_x < OFFSET_X || cnt_y < OFFSET_Y) flag_crop <= CROP_GIVE_UP;
else if (cnt_x < OFFSET_X + OUT_WIDTH && cnt_y < OFFSET_Y + OUT_HEIGHT) begin
if (cnt_x < IN_WIDTH && cnt_y < IN_HEIGHT) flag_crop <= CROP_KEEP;
else flag_crop <= CROP_BLANK;
end else flag_crop <= CROP_ERROR;
end
if (pipeline_valid[1]) begin
for (i = 0; i < 3; i++) out_data[i] <= data_cache1[i];
out_hsync <= (temp_x == OFFSET_X) && (temp_y >= OFFSET_Y);
out_fsync <= (temp_x == OFFSET_X) && (temp_y == OFFSET_Y);
case (flag_crop)
CROP_ERROR: {force_dis, force_en} <= {1'b1, 1'b0};
CROP_KEEP: {force_dis, force_en} <= {1'b0, 1'b0};
CROP_GIVE_UP: {force_dis, force_en} <= {1'b1, 1'b0};
CROP_BLANK:
{force_dis, force_en} <= {1'b0, 1'b0}; //应该是01, 但我还没写BLANK逻辑
endcase
end
end
end
endmodule

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`timescale 1ns / 1ps
module Demosaic #(
parameter WINDOW_LENGTH = 3,
parameter reg [15:0] TOTAL_WIDTH = 512+3, // 总图像宽度
parameter reg [15:0] TOTAL_HEIGHT = 256+3, // 总图像高度
parameter reg [ 1:0] RAW_TYPE = 3, // (0,0)位置算起RAW_TYPE的值
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
)(
input wire clk,
input wire reset,
input wire [DATA_WIDTH - 1:0] in_data [WINDOW_LENGTH*WINDOW_LENGTH], // 数据输入线.第一列数据在[0],[1],[2]中
output reg [DATA_WIDTH - 1:0] out_data [3], // 数据输出线，3、2、1分别表示r、g、b
input wire in_valid,
output wire out_valid,
input wire in_ready,
output wire out_ready,
output reg out_hsync, // 行同步，一行第一个像素点输出的同时高电平
output reg out_fsync // 帧同步，一帧第一个像素点输出的同时高电平
);
localparam DATA_NUM = WINDOW_LENGTH*WINDOW_LENGTH;
localparam PIPILINE = 3;
reg [PIPILINE-1:0] pipeline_valid;
wire pipeline_running;
assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = pipeline_running;
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = pipeline_valid[PIPILINE-1];
reg [DATA_WIDTH-1:0] data_cache[DATA_NUM]; // 缓存颜色数据，行列nxn
reg [31:0] pos_x, pos_y, temp_pos_x, temp_pos_y;
reg [DATA_WIDTH-1:0] red, blue, green;
reg [1:0] raw_type;
integer i;
always @(posedge clk) begin
if(reset) begin
for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= 0;
pipeline_valid <= 0;
{red, green, blue} <= 0;
{out_data[2],out_data[1],out_data[0]} <= 0;
{out_hsync,out_fsync} <= 0;
pos_x <= ~0;
pos_y <= ~0;
temp_pos_x <= 0;
temp_pos_y <= 0;
end else if(pipeline_running) begin
pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
if(in_valid) begin
for(i=0;i<DATA_NUM;i=i+1) data_cache[i] <= in_data[i];
pos_x <= (pos_x >= TOTAL_WIDTH - 1)?(0):(pos_x + 1);
pos_y <= (pos_x >= TOTAL_WIDTH - 1)?((pos_y >= TOTAL_HEIGHT - 1)?(0):(pos_y + 1)):(pos_y);
end
if(pipeline_valid[0]) begin
temp_pos_x <= pos_x;
temp_pos_y <= pos_y;
case (raw_type)
0: begin // Missing B, R on G
blue <= (data_cache[1] + data_cache[7]) >> 1;
red <= (data_cache[3] + data_cache[5]) >> 1;
green <= data_cache[4];
end
1: begin // Missing G, R on B
green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
red <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
blue <= data_cache[4];
end
2: begin // Missing G, B on R
green <= (data_cache[1] + data_cache[3] + data_cache[5] + data_cache[7]) >> 2;
blue <= (data_cache[0] + data_cache[2] + data_cache[6] + data_cache[8]) >> 2;
red <= data_cache[4];
end
3: begin // Missing B, R on G
red <= (data_cache[1] + data_cache[7]) >> 1;
blue <= (data_cache[3] + data_cache[5]) >> 1;
green <= data_cache[4];
end
endcase
end
if(pipeline_valid[1]) begin
{out_data[2],out_data[1],out_data[0]} <= {red,blue,green};
out_hsync <= (temp_pos_x == 0);
out_fsync <= ((temp_pos_x == 0) && (temp_pos_y == 0));
end
end
end
// 0:gr 1:rg 2:bg 3:gb 窗口右移，0<->1 2<->3; 窗口下移，0<->2，1<->3。
// bg gb gr rg
always @(*) begin
if(reset) raw_type = RAW_TYPE;
else case (RAW_TYPE)
2'b00: raw_type = {pos_y[0], pos_x[0]};
2'b01: raw_type = {pos_y[0], ~pos_x[0]};
2'b10: raw_type = {~pos_y[0], pos_x[0]};
2'b11: raw_type = {~pos_y[0], ~pos_x[0]};
endcase
end
endmodule

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`timescale 1ns / 1ps
module DiffWidthSyncFIFO #(
parameter reg [7:0] DATA_WIDTH = 8,
parameter reg [7:0] DATA_DEPTH = 12,
parameter reg [7:0] READ_DEPTH = 3,
parameter reg [7:0] WRITE_DEPTH = 4
) (
input wire clk,
input wire reset,
input wire read_ready,
output reg read_en,
output reg [DATA_WIDTH - 1 : 0] read_data[READ_DEPTH],
output wire write_ready,
input wire write_en,
input wire [DATA_WIDTH - 1 : 0] write_data[WRITE_DEPTH]
);
reg [DATA_WIDTH - 1 : 0] data[DATA_DEPTH];
reg [7:0] occupancy;
reg [7:0] cnt_read, cnt_write;
reg [7:0] wi, ri;
reg read_finish, write_finish;
always @(posedge clk or posedge reset) begin
if (reset) begin
occupancy <= 0;
end
else begin
if (read_finish && write_finish) begin
occupancy <= occupancy + (WRITE_DEPTH - READ_DEPTH);
end
else if (read_finish) begin
occupancy <= occupancy - READ_DEPTH;
end
else if (write_finish) begin
occupancy <= occupancy + WRITE_DEPTH;
end
else begin
occupancy <= occupancy;
end
end
end
// write data to fifo
assign write_ready = ((DATA_DEPTH - occupancy) >= WRITE_DEPTH && !write_en) ? 1 : 0;
always @(posedge clk or posedge reset) begin
if (reset) begin
cnt_write <= 0;
wi <= 0;
write_finish <= 0;
end else begin
if (write_en && (DATA_DEPTH - occupancy) >= WRITE_DEPTH) begin
for (wi = 0; wi < WRITE_DEPTH; wi = wi + 1) begin
data[cnt_write] <= write_data[wi];
if (cnt_write < DATA_DEPTH - 1) cnt_write <= cnt_write + 1;
else cnt_write <= 0;
end
write_finish <= 1;
end else begin
write_finish <= 0;
end
end
end
integer i;
always @(posedge clk or posedge reset) begin
if (reset) begin
for (i = 0; i < READ_DEPTH; i = i + 1) begin
read_data[i] <= 0;
end
ri <= 0;
read_en <= 0;
cnt_read <= 0;
read_finish <= 0;
end else begin
if (read_ready && occupancy >= READ_DEPTH) begin
read_en <= 1;
for (ri = 0; ri < READ_DEPTH; ri = ri + 1) begin
read_data[ri] <= data[cnt_read];
if (cnt_read < DATA_DEPTH - 1) cnt_read <= cnt_read + 1;
else cnt_read <= 0;
end
read_finish <= 1;
end else begin
read_en <= 0;
read_finish <= 0;
end
end
end
endmodule

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`timescale 1ns/1ps
module RGB_to_RAM #(
parameter COLOR_DEPTH = 8,
parameter FIFO_SIZE = 128
) (
input clk,
input reset,
// 数据输入
output reg in_que,
input in_en,
input [3 * COLOR_DEPTH - 1:0] data_in,
// 写入SRAM
input write_que,
output write_en,
output [15:0] data_write
);
// 状态机
localparam READ_DATA = 0;
localparam SEND_R = 1;
localparam SEND_GB = 2;
reg [2:0] state, nextState;
reg [3 * COLOR_DEPTH - 1:0] data_cache;
reg [15:0] fifo_data;
wire fifo_full, fifo_empty;
async_fifo #(
.DSIZE(16),
.ASIZE(FIFO_SIZE)
) fifo_image (
.wclk(clk),
.wrst_n(reset),
.rclk(clk),
.rrst_n(reset),
.winc(in_en),
.wdata(fifo_data),
.wfull(fifo_full),
/* verilator lint_off PINCONNECTEMPTY */
.awfull(),
.rinc(write_en),
.rdata(data_write),
.rempty(fifo_empty),
/* verilator lint_off PINCONNECTEMPTY */
.arempty()
);
// 当有数据请求且FIFO不为空时，输出数据
assign write_en = (write_que && !fifo_empty) ? 1 : 0;
always @(posedge clk or posedge reset) begin
if (reset)
state <= READ_DATA;
else
state <= nextState;
end
always @(posedge clk or posedge reset) begin
if (reset) begin
fifo_data <= 0;
data_cache <= 0;
end
else begin
case (state)
// 读取数据
READ_DATA: begin
in_que <= 1;
if (in_en) begin
data_cache <= data_in;
nextState <= SEND_R;
end
end
SEND_R: begin
in_que <= 0;
fifo_data <= {8'b0, data_cache[3 * COLOR_DEPTH - 1:16]};
nextState <= SEND_GB;
end
SEND_GB: begin
fifo_data <= data_cache[15:0];
nextState <= READ_DATA;
end
endcase
end
end
endmodule

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module SDRAM (
input wire clk,
input wire read_en,
input wire [31:0] read_addr,
output wire [31:0] read_data,
output wire read_ready,
input wire write_en,
input wire [31:0] write_addr,
input reg [31:0] write_data,
output wire write_ready
);
reg [31:0] ram[1920*1080];
assign read_ready = (!read_en) ? 1 : 0;
assign write_ready = (!write_en) ? 1 : 0;
always @(posedge clk) begin
if (read_en)
ram[read_addr] <= read_data;
end
always @(posedge clk) begin
if (write_en)
write_data <= ram[write_addr];
end
endmodule

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`timescale 1ns / 1ps
`include "DiffWidthSyncFIFO.v"
`default_nettype none
module tb_DiffWidthSyncFIFO;
localparam reg [7:0] DATA_WIDTH = 8;
localparam reg [7:0] DATA_DEPTH = 12;
localparam reg [7:0] READ_DEPTH = 3;
localparam reg [7:0] WRITE_DEPTH = 4;
reg clk;
reg reset;
reg write_en;
reg [DATA_WIDTH - 1 : 0] write_data[WRITE_DEPTH];
wire read_en, write_ready, read_ready;
wire [DATA_WIDTH - 1 : 0] read_data[READ_DEPTH];
DiffWidthSyncFIFO #(
.DATA_WIDTH (DATA_WIDTH),
.DATA_DEPTH (DATA_DEPTH),
.READ_DEPTH (READ_DEPTH),
.WRITE_DEPTH(WRITE_DEPTH)
) inst_fifo (
.clk (clk),
.reset(reset),
.read_ready(read_ready),
.read_en(read_en),
.read_data(read_data),
.write_ready(write_ready),
.write_en(write_en),
.write_data(write_data)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
$dumpfile("tb_DiffWidthSyncFIFO.vcd");
$dumpvars(0, tb_DiffWidthSyncFIFO);
end
assign read_ready = read_en ? 0 : 1;
integer j;
initial begin
clk = 0;
reset = 1;
write_en = 0;
for(j = 0; j < WRITE_DEPTH; j = j + 1)begin
write_data[j] = 0;
end
end
integer i;
initial begin
#(10 * CLK_PERIOD) reset = 0;
for (i = 0; i < 20; i = i + 1) begin
#CLK_PERIOD
for (j = 0; j < WRITE_DEPTH; j = j + 1) begin
write_data[j] = {$mti_random} % (32'b1 << DATA_DEPTH);
end
write_en = 1;
#CLK_PERIOD write_en = 0;
end
$finish(100 * CLK_PERIOD);
end
endmodule
`default_nettype wire

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`timescale 1ns / 1ps
module Windows #(
parameter reg [ 4:0] DATA_WIDTH = 16 // 输入/输出数据位宽
)(
// 基本信号
input wire clk,
input wire reset,
// 数据线
input wire [DATA_WIDTH - 1:0] in_data [3], // 0、1、2分别表示第一、二、三行
output reg [DATA_WIDTH - 1:0] out_data [3*3], // 数据输出线
// 有效信号
input wire in_valid, // 上一模块输出数据有效
output wire out_valid, // 当前模块输出数据有效
// 准备信号
input wire in_ready, // 下一模块可接受新数据
output wire out_ready // 当前模块可接收新数据
);
localparam PIPILINE = 3;
reg [PIPILINE-1:0] pipeline_valid;
//out_ready ：只要本模块可以接收数据就一直拉高
assign out_ready = (pipeline_valid != {PIPILINE{1'b1}}) | ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready);
//out_valid ：只要本模块可以发出数据就一直拉高
assign out_valid = (pipeline_valid == {PIPILINE{1'b1}});
integer i;
always @(posedge clk) begin
if(reset) begin
for(i=0;i<9;i=i+1) out_data[i] <= 0;
pipeline_valid <= 0;
end else begin
if((pipeline_valid != {PIPILINE{1'b1}}) || ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready))begin
pipeline_valid[0] <= in_valid;
out_data[6] <= in_data[0];
out_data[7] <= in_data[1];
out_data[8] <= in_data[2];
end
if((pipeline_valid[2] == 0) || (pipeline_valid[1] == 0) || ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready))begin
pipeline_valid[1] <= pipeline_valid[0];
out_data[3] <= out_data[6];
out_data[4] <= out_data[7];
out_data[5] <= out_data[8];
end
if((pipeline_valid[2] == 0) || ((pipeline_valid == {PIPILINE{1'b1}}) && in_ready))begin
pipeline_valid[2] <= pipeline_valid[1];
out_data[0] <= out_data[3];
out_data[1] <= out_data[4];
out_data[2] <= out_data[5];
end
end
end
endmodule

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`timescale 1ns / 1ps
module isp #(
parameter reg [15:0] IN_WIDTH = 1936,
parameter reg [15:0] IN_HEIGHT = 1088,
parameter OFFSET_X = 7,
parameter OFFSET_Y = 3,
parameter reg [15:0] OUT_WIDTH = 1920,
parameter reg [15:0] OUT_HEIGHT = 1080,
parameter reg [ 4:0] COLOR_DEPTH = 8, // Can't Change!!!
parameter reg [ 1:0] RAW_TYPE = 3 // 0:grbg 1:rggb 2:bggr 3:gbrg
) (
// 基本信号
input wire clk,
input wire reset,
// 数据线
input wire [15:0] in_data[3], // 数据输入线，0、1、2分别表示第一、二、三行
output wire [3 * COLOR_DEPTH - 1:0] out_data,
// 数据有效信号
input wire in_valid,
output wire out_valid,
// 准备信号
input wire in_ready,
output wire out_ready,
// 颜色校正，低八位为小数位，高八位为整数位
input wire [15:0] gain_red,
input wire [15:0] gain_green,
input wire [15:0] gain_blue,
input wire blender_enable // 是否启用颜色校正
);
wire [15:0] Demosaic2_data[3];
wire [15:0] Windows_data[9];
wire [COLOR_DEPTH - 1 : 0] Blender_data[3];
wire [COLOR_DEPTH - 1 : 0] Crop_data[3];
wire Windows_valid, Demosaic2_valid, Blender_valid, Crop_valid;
wire Windows_ready, Demosaic2_ready, Blender_ready, Crop_ready;
wire Demosaic2_hsync, Blender_hsync, Crop_hsync;
wire Demosaic2_fsync, Blender_fsync, Crop_fsync;
assign out_valid = Crop_valid;
assign out_ready = Windows_ready;
assign out_data = {Crop_data[2], Crop_data[1], Crop_data[0]};
Windows #(
.DATA_WIDTH(16)
) Windows_inst (
.clk (clk),
.reset (reset),
.in_data (in_data),
.out_data (Windows_data),
.in_valid (in_valid),
.out_valid(Windows_valid),
.in_ready (Demosaic2_ready),
.out_ready(Windows_ready)
);
Demosaic #(
.WINDOW_LENGTH(3),
.TOTAL_WIDTH (IN_WIDTH),
.TOTAL_HEIGHT (IN_HEIGHT),
.RAW_TYPE (RAW_TYPE),
.DATA_WIDTH (16)
) Demosaic2_inst (
.clk (clk),
.reset (reset),
.in_data (Windows_data),
.out_data (Demosaic2_data),
.in_valid (Windows_valid),
.out_valid(Demosaic2_valid),
.in_ready (Blender_ready),
.out_ready(Demosaic2_ready),
.out_hsync(Demosaic2_hsync),
.out_fsync(Demosaic2_fsync)
);
ColorBlender #(
.IN_DEPTH(12), // 输入图像的色深
.OUT_DEPTH(COLOR_DEPTH) // 输出图像的色深
) ColorBlender_inst (
.clk (clk),
.reset (reset),
.in_data (Demosaic2_data),
.out_data (Blender_data),
.in_valid (Demosaic2_valid),
.out_valid(Blender_valid),
.in_ready (Crop_ready),
.out_ready(Blender_ready),
.in_hsync (Demosaic2_hsync),
.in_fsync (Demosaic2_fsync),
.out_hsync(Blender_hsync),
.out_fsync(Blender_fsync),
.gain_red (gain_red),
.gain_green(gain_green),
.gain_blue (gain_blue),
.enable (blender_enable)
);
Crop #(
.IN_WIDTH (IN_WIDTH),
.IN_HEIGHT (IN_HEIGHT),
.OFFSET_X (OFFSET_X),
.OFFSET_Y (OFFSET_Y),
.OUT_WIDTH (OUT_WIDTH),
.OUT_HEIGHT (OUT_HEIGHT),
.COLOR_DEPTH(COLOR_DEPTH)
) Crop_inst (
.clk (clk),
.reset (reset),
.in_data (Blender_data),
.out_data (Crop_data),
.in_valid (Blender_valid),
.out_valid(Crop_valid),
.in_ready (in_ready),
.out_ready(Crop_ready),
.in_hsync (Blender_hsync),
.in_fsync (Blender_fsync),
.out_hsync(Crop_hsync),
.out_fsync(Crop_fsync)
);
// reg [15:0] data_out_temp[8192];
// reg [31:0] now;
// reg [2:0] cnt_www;
// reg flag_ifdataerror;
// initial cnt_www = 0;
// always @(posedge reset) begin
// cnt_www <= cnt_www + 1;
// end
// integer i;
// always @(posedge clk) begin
// if(reset) begin
// flag_ifdataerror <= 0;
// if(cnt_www==1) for(i=0;i<8192;i=i+1) data_out_temp[i] <= 0;
// now <= 0;
// end else if(Crop_valid && in_ready)begin
// now <= now + 1;
// if(cnt_www==1)begin
// if(now<8192) data_out_temp[now] <= Crop_data[0];
// end else if(cnt_www==2)begin
// flag_ifdataerror <= (data_out_temp[now] != Crop_data[0]);
// end else flag_ifdataerror <= flag_ifdataerror;
// end
// end
endmodule

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`timescale 1ns / 1ps
module isp_tb();
parameter IN_WIDTH = 50;
parameter IN_HEIGHT = 50;
parameter OFFSET_X = 7;
parameter OFFSET_Y = 3;
parameter OUT_WIDTH = 30;
parameter OUT_HEIGHT = 30;
parameter COLOR_DEPTH = 8;
parameter RAW_TYPE = 3;
reg clk;
initial clk = 0;
always #20 clk <= ~clk;
reg[31:0] cnt_www;
reg reset;
initial begin
reset = 1;
cnt_www = 700;
#500
reset = 0;
#5000000
reset = 1;
cnt_www = 2000;
#500
reset = 0;
end
reg [15:0] in_data[3];
wire [23:0]out_data;
reg in_valid;
wire out_valid;
reg in_ready;
wire out_ready;
reg[31:0] cnt_valid, cnt_ready;
integer i;
always @(posedge clk) begin
if(reset) begin
in_valid <= 0;
in_ready <= 0;
cnt_valid <= 10;
cnt_ready <= 0;
for(i=0;i<3;i=i+1) in_data[i] <= 0;
end else begin
cnt_valid <= cnt_valid+1;
cnt_ready <= cnt_ready+1;
if(cnt_ready==cnt_www)begin
cnt_ready <= 0;
in_ready <= ~in_ready;
end
if(cnt_valid==500)begin
cnt_valid <= 200;
in_valid <= ~in_valid;
end
if(in_valid && out_ready)begin
in_data[0] <= in_data[0] + 1;
for(i=1;i<3;i=i+1) in_data[i] <= in_data[i-1];
end
end
end
reg [23:0] data_out_temp[8192*5];
reg [31:0] now;
reg flag_ifdataerror;
always @(posedge clk) begin
if(reset) begin
flag_ifdataerror <= 0;
if(cnt_www==700) for(i=0;i<(1<<32);i=i+1) data_out_temp[i] <= 0;
now <= 0;
end else if(out_valid && in_ready)begin
now <= now + 1;
if(cnt_www==700)begin
data_out_temp[now] <= out_data;
end else if(cnt_www==2000)begin
flag_ifdataerror <= (data_out_temp[now] != out_data);
end else flag_ifdataerror <= flag_ifdataerror;
end
end
isp_nofifo
#(
.IN_WIDTH (IN_WIDTH ),
.IN_HEIGHT (IN_HEIGHT ),
.OFFSET_X (OFFSET_X ),
.OFFSET_Y (OFFSET_Y ),
.OUT_WIDTH (OUT_WIDTH ),
.OUT_HEIGHT (OUT_HEIGHT ),
.COLOR_DEPTH (COLOR_DEPTH ),
.RAW_TYPE (RAW_TYPE )
)
u_isp(
.clk (clk ),
.reset (reset ),
.in_data (in_data ),
.out_data (out_data ),
.in_valid (in_valid ),
.out_valid (out_valid ),
.in_ready (in_ready ),
.out_ready (out_ready ),
.gain_red (50 ),
.gain_green (50 ),
.gain_blue (50 ),
.blender_enable (0 )
);
endmodule