100 lines
3.3 KiB
Systemverilog
100 lines
3.3 KiB
Systemverilog
`timescale 1ns / 1ps
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// 三通道图像合成一个RGB图像
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module ColorBlender #(
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parameter reg [4:0] IN_DEPTH = 12, // 输入图像的色深
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parameter reg [4:0] OUT_DEPTH = 8 // 输出图像的色深
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) (
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input wire clk,
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input wire reset,
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input wire [16 - 1:0] in_data [3],
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output reg [OUT_DEPTH - 1:0] out_data [3],
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input wire in_valid,
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output wire out_valid,
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input wire in_ready,
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output wire out_ready,
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input wire in_hsync,
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input wire in_fsync,
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output wire out_hsync,
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output wire out_fsync,
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// 颜色校正
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input wire [15:0] gain_red,
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input wire [15:0] gain_green,
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input wire [15:0] gain_blue,
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input wire enable
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);
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localparam PIPELINE = 4;
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reg [PIPELINE-1:0] pipeline_hsync, pipeline_fsync, pipeline_valid;
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wire pipeline_flag;
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assign pipeline_flag = (pipeline_valid[PIPELINE-1] == 0) | (in_ready);
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//out_ready :只要本模块可以接收数据就一直拉高
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assign out_ready = pipeline_flag;
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//out_valid :只要本模块有数据要发送就一直拉高
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assign out_valid = pipeline_valid[PIPELINE-1];
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assign out_hsync = pipeline_hsync[PIPELINE-1];
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assign out_fsync = pipeline_fsync[PIPELINE-1];
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reg [32 - 1:0] data_cal0[3];
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reg [32 - 1:0] data_cal1[3];
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reg [32 - 1:0] data_cal2[3];
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integer i;
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always @(posedge clk) begin
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if(reset) begin
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pipeline_valid <= 0;
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pipeline_hsync <= 0;
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pipeline_fsync <= 0;
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for(i=0;i<3;i=i+1) data_cal0[i] <= 0;
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for(i=0;i<3;i=i+1) data_cal1[i] <= 0;
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for(i=0;i<3;i=i+1) data_cal2[i] <= 0;
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for(i=0;i<3;i=i+1) out_data[i] <= 0;
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end else if(pipeline_flag) begin
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/************* 流水 ************/
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pipeline_valid <= {pipeline_valid[PIPELINE-2:0], in_valid};
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pipeline_hsync <= {pipeline_hsync[PIPELINE-2:0], in_hsync};
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pipeline_fsync <= {pipeline_fsync[PIPELINE-2:0], in_fsync};
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/************* 1:计算1 ************/
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if(in_valid) begin
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data_cal0[0] <= ({16'b0, in_data[0]}) << (8 - (IN_DEPTH - OUT_DEPTH));
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data_cal0[1] <= ({16'b0, in_data[1]}) << (8 - (IN_DEPTH - OUT_DEPTH));
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data_cal0[2] <= ({16'b0, in_data[2]}) << (8 - (IN_DEPTH - OUT_DEPTH));
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end
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/************* 2:计算2 ************/
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if(pipeline_valid[0]) begin
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if(enable) begin
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data_cal1[0] <= (data_cal0[0] * {16'b0, gain_red}) >> 16;
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data_cal1[1] <= (data_cal0[1] * {16'b0, gain_green}) >> 16;
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data_cal1[2] <= (data_cal0[2] * {16'b0, gain_blue}) >> 16;
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end else begin
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data_cal1[0] <= data_cal0[0] >> 8;
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data_cal1[1] <= data_cal0[1] >> 8;
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data_cal1[2] <= data_cal0[2] >> 8;
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end
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end
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/************* 3:计算3 ************/
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if(pipeline_valid[1]) begin
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data_cal2[0] <= (data_cal1[0][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[0];
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data_cal2[1] <= (data_cal1[1][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[1];
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data_cal2[2] <= (data_cal1[2][31 : OUT_DEPTH] != 0) ? {32{1'b1}} : data_cal1[2];
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end
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/************* 4:发送结果 ************/
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if(pipeline_valid[2]) begin
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out_data[0] <= data_cal2[0][OUT_DEPTH-1:0];
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out_data[1] <= data_cal2[1][OUT_DEPTH-1:0];
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out_data[2] <= data_cal2[2][OUT_DEPTH-1:0];
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end
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end
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end
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endmodule
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