75 lines
1.6 KiB
Systemverilog
Executable File
75 lines
1.6 KiB
Systemverilog
Executable File
`timescale 1ns / 1ps
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`include "DiffWidthSyncFIFO.v"
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`default_nettype none
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module tb_DiffWidthSyncFIFO;
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localparam reg [7:0] DATA_WIDTH = 8;
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localparam reg [7:0] DATA_DEPTH = 12;
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localparam reg [7:0] READ_DEPTH = 3;
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localparam reg [7:0] WRITE_DEPTH = 4;
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reg clk;
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reg reset;
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reg write_en;
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reg [DATA_WIDTH - 1 : 0] write_data[WRITE_DEPTH];
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wire read_en, write_ready, read_ready;
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wire [DATA_WIDTH - 1 : 0] read_data[READ_DEPTH];
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DiffWidthSyncFIFO #(
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.DATA_WIDTH (DATA_WIDTH),
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.DATA_DEPTH (DATA_DEPTH),
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.READ_DEPTH (READ_DEPTH),
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.WRITE_DEPTH(WRITE_DEPTH)
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) inst_fifo (
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.clk (clk),
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.reset(reset),
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.read_ready(read_ready),
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.read_en(read_en),
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.read_data(read_data),
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.write_ready(write_ready),
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.write_en(write_en),
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.write_data(write_data)
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);
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localparam CLK_PERIOD = 10;
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always #(CLK_PERIOD / 2) clk = ~clk;
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initial begin
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$dumpfile("tb_DiffWidthSyncFIFO.vcd");
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$dumpvars(0, tb_DiffWidthSyncFIFO);
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end
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assign read_ready = read_en ? 0 : 1;
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integer j;
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initial begin
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clk = 0;
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reset = 1;
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write_en = 0;
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for(j = 0; j < WRITE_DEPTH; j = j + 1)begin
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write_data[j] = 0;
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end
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end
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integer i;
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initial begin
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#(10 * CLK_PERIOD) reset = 0;
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for (i = 0; i < 20; i = i + 1) begin
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#CLK_PERIOD
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for (j = 0; j < WRITE_DEPTH; j = j + 1) begin
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write_data[j] = {$mti_random} % (32'b1 << DATA_DEPTH);
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end
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write_en = 1;
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#CLK_PERIOD write_en = 0;
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end
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$finish(100 * CLK_PERIOD);
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end
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endmodule
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`default_nettype wire
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