ISP/rtl/RAM/tb_DiffWidthSyncFIFO.sv

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`timescale 1ns / 1ps
`include "DiffWidthSyncFIFO.v"
`default_nettype none
module tb_DiffWidthSyncFIFO;
localparam reg [7:0] DATA_WIDTH = 8;
localparam reg [7:0] DATA_DEPTH = 12;
localparam reg [7:0] READ_DEPTH = 3;
localparam reg [7:0] WRITE_DEPTH = 4;
reg clk;
reg reset;
reg write_en;
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reg [DATA_WIDTH - 1 : 0] write_data[WRITE_DEPTH];
wire read_en, write_ready, read_ready;
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wire [DATA_WIDTH - 1 : 0] read_data[READ_DEPTH];
DiffWidthSyncFIFO #(
.DATA_WIDTH (DATA_WIDTH),
.DATA_DEPTH (DATA_DEPTH),
.READ_DEPTH (READ_DEPTH),
.WRITE_DEPTH(WRITE_DEPTH)
) inst_fifo (
.clk (clk),
.reset(reset),
.read_ready(read_ready),
.read_en(read_en),
.read_data(read_data),
.write_ready(write_ready),
.write_en(write_en),
.write_data(write_data)
);
localparam CLK_PERIOD = 10;
always #(CLK_PERIOD / 2) clk = ~clk;
initial begin
$dumpfile("tb_DiffWidthSyncFIFO.vcd");
$dumpvars(0, tb_DiffWidthSyncFIFO);
end
assign read_ready = read_en ? 0 : 1;
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integer j;
initial begin
clk = 0;
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reset = 1;
write_en = 0;
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for(j = 0; j < WRITE_DEPTH; j = j + 1)begin
write_data[j] = 0;
end
end
integer i;
initial begin
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#(10 * CLK_PERIOD) reset = 0;
for (i = 0; i < 20; i = i + 1) begin
#CLK_PERIOD
for (j = 0; j < WRITE_DEPTH; j = j + 1) begin
write_data[j] = {$mti_random} % (32'b1 << DATA_DEPTH);
end
write_en = 1;
#CLK_PERIOD write_en = 0;
end
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$finish(100 * CLK_PERIOD);
end
endmodule
`default_nettype wire