ISP/isp.v

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`timescale 1ns / 1ps
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module isp #(
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parameter IN_WIDTH = 1936,
parameter IN_HEIGHT = 1088,
parameter OUT_WIDTH = 1920,
parameter OUT_HEIGHT = 1080,
parameter COLOR_DEPTH = 8,
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parameter RAW_TYPE = 3 // 0:grbg 1:rggb 2:bggr 3:gbrg
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) (
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// 基本信号
input wire clk,
input wire reset,
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// 数据输入信号
input wire data_en,
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input reg [15:0] data_in[2:0], // 数据输入线012分别表示第一三行
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output reg data_que, // 数据请求线高电平请求三个数据直到读取完才拉低
output wire out_clk,
output wire out_en,
output reg [3 * COLOR_DEPTH - 1:0] data_out,
input wire color_correction
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);
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localparam BAYER_WIDTH = IN_WIDTH - 2;
localparam BAYER_HEIGHT = IN_HEIGHT - 2;
// 三通道合成RGB图像
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wire blender_en, blender_ready, blender_receive;
wire [15:0] blender_r, blender_g, blender_b;
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// 任意比例缩放图像
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wire crop_en, crop_ready, crop_receive; // scaler 请求数据
reg [3 * COLOR_DEPTH - 1:0] crop_data;
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// 写入RAM
// wire RAM_in_en;
// wire RAM_in_que; // RAM 请求数据
// wire [3 * COLOR_DEPTH - 1:0] RAM_in_data;
always @(clk) out_clk <= clk;
demosaic2 #(
.IM_WIDTH (IN_WIDTH),
.IM_HEIGHT(IN_HEIGHT),
.RAW_TYPE (RAW_TYPE)
) CFA (
.clk(clk),
.reset(reset),
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.in_en(data_en),
.in_data(data_in),
.out_ready(data_que),
.out_en(blender_en),
.out_receive(),
.out_en(blender_en),
.in_ready(blender_ready),
.in_receive(blender_receive),
.out_r(blender_r),
.out_g(blender_g),
.out_b(blender_b)
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);
ColorBlender #(
.IN_DEPTH (12),
.OUT_DEPTH(8),
.GAIN_RED(120),
.GAIN_GREEN(50),
.GAIN_BLUE(95),
) blender (
.clk(clk),
.reset(reset),
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.in_en(blender_en),
.in_data({blender_r, blender_g, blender_b}),
.out_ready(blender_ready),
.out_receive(blender_receive),
.in_ready(crop_ready),
.in_receive(crop_receive)
.out_en(crop_en),
.data_out(crop_data),
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.color_correction(color_correction)
);
crop #(
.IN_WIDTH(BAYER_WIDTH),
.IN_HEIGHT(BAYER_HEIGHT),
.OUT_WIDTH(OUT_WIDTH),
.OUT_HEIGHT(OUT_HEIGHT),
.COLOR_DEPTH(COLOR_DEPTH)
) crop_process (
.clk (clk),
.reset(reset),
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.in_en (crop_en),
.out_ready (crop_ready),
.out_receive(crop_receive)
.in_data(crop_data),
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.out_en (out_en),
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.in_ready(),
.in_receive(),
.out_data(data_out)
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);
// RGB_to_RAM write_to_RAM (
// .clk(clk),
// .reset(reset),
// .in_en(RAM_in_en),
// .in_que(RAM_in_que),
// .data_in(RAM_in_data),
// .write_que(out_que),
// .write_en(out_en),
// .data_write(data_out)
// );
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endmodule