36 lines
1.0 KiB
Verilog
36 lines
1.0 KiB
Verilog
`timescale 1ns/1ps
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// 三通道图像合成一个RGB图像
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module chanels_to_RGB #(
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parameter IN_DEPTH = 12, // 输入图像的色深
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parameter OUT_DEPTH = 8 // 输出图像的色深
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) (
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input clk,
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input reset,
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input in_en,
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input [IN_DEPTH - 1:0] data_in [2:0], // 0:R 1:G 2:B
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output reg out_en,
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output reg [3 * OUT_DEPTH - 1:0] data_out
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);
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reg [31:0] data_cal [2:0]; // 用于保存运算结果，防止溢出
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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// 初始化
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out_en <= 0;
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data_out <= 0;
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end
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else begin
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if (in_en) begin
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data_cal[0] <= data_in[0] * OUT_DEPTH / IN_DEPTH;
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data_cal[1] <= data_in[1] * OUT_DEPTH / IN_DEPTH;
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data_cal[2] <= data_in[2] * OUT_DEPTH / IN_DEPTH;
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data_out <= {data_cal[0][OUT_DEPTH - 1:0], data_cal[1][OUT_DEPTH - 1:0],data_cal[2][OUT_DEPTH - 1:0]};
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end
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out_en <= in_en;
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end
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end
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endmodule |