107 lines
3.4 KiB
Systemverilog
107 lines
3.4 KiB
Systemverilog
`timescale 1ns / 1ps
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module Crop_Pipeline #(
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parameter IN_WIDTH = 512,
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parameter IN_HEIGHT = 512,
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parameter OFFSET_X = 120,
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parameter OFFSET_Y = 256,
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// parameter TRANSLAYT_X = 120,
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// parameter TRANSLAYT_Y = 120,
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parameter OUT_WIDTH = 512,
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parameter OUT_HEIGHT = 512,
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parameter BLANK_COLOR = 6'h000000,
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parameter COLOR_DEPTH = 16
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) (
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input wire clk,
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input wire reset,
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input wire [COLOR_DEPTH - 1:0] in_data [3],
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output reg [COLOR_DEPTH - 1:0] out_data[3],
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input wire in_valid,
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output reg out_valid,
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input wire in_ready,
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output wire out_ready,
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input wire in_hsync,
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input wire in_fsync,
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output reg out_hsync,
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output reg out_fsync
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);
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localparam PIPILINE = 3;
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reg [PIPILINE-1:0] pipeline_valid;
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wire pipeline_running;
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assign pipeline_running = in_ready | ~pipeline_valid[PIPILINE-1];
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reg [31:0] cnt_x, cnt_y, temp_x, temp_y;
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reg force_dis, force_en;
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reg [COLOR_DEPTH-1:0] data_cache0[3];
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reg [COLOR_DEPTH-1:0] data_cache1[3];
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//out_ready ：只要本模块可以接收数据就一直拉高
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assign out_ready = pipeline_running;
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//out_valid ：只要本模块可以发出数据就一直拉高
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assign out_valid = (pipeline_valid[PIPILINE-1] & ~force_dis) | force_en;
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//分别表示当前像素: 显示；被裁掉；空。
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reg [1:0] flag_crop;
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localparam CROP_ERROR = 2'b00, CROP_KEEP = 2'b01, CROP_GIVE_UP = 2'b10, CROP_BLANK = 2'b11;
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integer i;
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always @(posedge clk) begin
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if (reset) begin
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pipeline_valid <= 0;
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cnt_x <= 0;
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cnt_y <= 0;
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for (i = 0; i < 3; i++) data_cache0[i] <= 0;
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for (i = 0; i < 3; i++) data_cache1[i] <= 0;
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for (i = 0; i < 3; i++) out_data[i] <= 0;
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flag_crop <= 0;
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force_dis <= 0;
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force_en <= 0;
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out_hsync <= 0;
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out_fsync <= 0;
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temp_x <= 0;
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temp_y <= 0;
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end else if (pipeline_running) begin
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pipeline_valid <= {pipeline_valid[PIPILINE-2:0], in_valid};
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if (in_valid) begin //when 00
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for (i = 0; i < 3; i++) data_cache0[i] <= in_data[i];
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cnt_x <= (in_hsync) ? (0) : (cnt_x + 1);
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cnt_y <= (in_hsync) ? ((in_fsync) ? (0) : (cnt_y + 1)) : (cnt_y);
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end
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if (pipeline_valid[0]) begin //when 00
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for (i = 0; i < 3; i++) data_cache1[i] <= data_cache0[i];
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temp_x <= cnt_x;
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temp_y <= cnt_y;
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if (cnt_x < OFFSET_X || cnt_y < OFFSET_Y) flag_crop <= CROP_GIVE_UP;
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else if (cnt_x < OFFSET_X + OUT_WIDTH && cnt_y < OFFSET_Y + OUT_HEIGHT) begin
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if (cnt_x < IN_WIDTH && cnt_y < IN_HEIGHT) flag_crop <= CROP_KEEP;
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else flag_crop <= CROP_BLANK;
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end else flag_crop <= CROP_ERROR;
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end
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if (pipeline_valid[1]) begin
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for (i = 0; i < 3; i++) out_data[i] <= data_cache1[i];
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out_hsync <= (temp_x == OFFSET_X) && (temp_y >= OFFSET_Y);
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out_fsync <= (temp_x == OFFSET_X) && (temp_y == OFFSET_Y);
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case (flag_crop)
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CROP_ERROR: {force_dis, force_en} <= {1'b1, 1'b0};
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CROP_KEEP: {force_dis, force_en} <= {1'b0, 1'b0};
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CROP_GIVE_UP: {force_dis, force_en} <= {1'b1, 1'b0};
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CROP_BLANK:
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{force_dis, force_en} <= {1'b0, 1'b0}; //应该是01, 但我还没写BLANK逻辑
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endcase
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end
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end
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end
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endmodule
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