87 lines
2.2 KiB
Verilog
87 lines
2.2 KiB
Verilog
`timescale 1ns / 1ps
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// 三通道图像合成一个RGB图像
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module ColorBlender #(
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parameter reg [ 4:0] IN_DEPTH = 12, // 输入图像的色深
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parameter reg [ 4:0] OUT_DEPTH = 8, // 输出图像的色深
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parameter reg [12:0] GAIN_RED = 120, // 红色增益系数(除以10^小数位数)
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parameter reg [12:0] GAIN_GREEN = 50, // 绿色增益系数
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parameter reg [12:0] GAIN_BLUE = 95, // 蓝色增益系数
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parameter reg [ 4:0] GAIN_OFFSET = 7
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) (
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input clk,
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input reset,
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input in_en,
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input [15:0] data_in[2], // 0:R 1:G 2:B
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output out_ready,
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output out_receive,
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// 输出相关
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input in_ready,
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input in_receive,
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output out_en,
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output [3 * OUT_DEPTH - 1:0] data_out,
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// 颜色校正
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input wire color_correction
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);
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localparam READ_DATA = 0;
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localparam CALC_DATA = 1;
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localparam SEND_DATA = 2;
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reg [2:0] state, nextState;
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reg [31:0] data_cal[2]; // 用于保存运算结果，防止溢出
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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state <= READ_DATA;
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end else begin
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state <= nextState;
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end
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end
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always @(*) begin
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case (state)
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READ_DATA: nextState = (in_en) ? (color_correction ? CALC_DATA : SEND_DATA) : READ_DATA;
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CALC_DATA: nextState = SEND_DATA;
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SEND_DATA: nextState = READ_DATA;
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default: nextState = READ_DATA;
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endcase
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end
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assign out_ready = (state == READ_DATA) ? 1 : 0;
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assign out_receive = in_en ? 1 : 0;
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assign out_en = (in_ready && state == SEND_DATA) ? 1 : 0;
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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// 初始化
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data_cal[0] <= 0;
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data_cal[1] <= 0;
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data_cal[2] <= 0;
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end else begin
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case (state)
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READ_DATA: begin
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if (in_en) begin
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data_cal[0] <= ({{(32 - IN_DEPTH){1'b0}}, data_in[0]} >> (IN_DEPTH - OUT_DEPTH));
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data_cal[1] <= ({{(32 - IN_DEPTH){1'b0}}, data_in[1]} >> (IN_DEPTH - OUT_DEPTH));
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data_cal[2] <= ({{(32 - IN_DEPTH){1'b0}}, data_in[2]} >> (IN_DEPTH - OUT_DEPTH));
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end
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end
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CALC_DATA: begin
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end
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SEND_DATA: begin
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end
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default: ;
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endcase
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end
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end
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endmodule
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