SikongJueluo
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ISP
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SystemVerilog 62.7%
C++ 23.2%
Makefile 6.2%
Verilog 4.2%
Nix 2.2%
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SikongJueluo 87d73b203a
reconstruct some modules 		2024-06-27 21:52:46 +08:00
ColorBlender reconstruct some modules 2024-06-27 21:52:46 +08:00
Crop add color correction function into chanels to RGB 2024-05-20 18:46:26 +08:00
Demosaic reconstruct some modules 2024-06-27 21:52:46 +08:00
RAM finish isp testbench but still have some errors waiting to be deat with 2024-05-15 16:35:17 +08:00
Scaler update scaler and RAM 2024-05-11 21:53:35 +08:00
sim reconstruct some modules 2024-06-27 21:52:46 +08:00
.gitignore update software sim 2024-05-18 18:56:32 +08:00
isp.v reconstruct some modules 2024-06-27 21:52:46 +08:00
xmake.lua reconstruct some modules 2024-06-27 21:52:46 +08:00