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SikongJueluo 7833c3a7b5 just make a little part of saturation correction

2024-06-29 21:31:58 +08:00

Color

just make a little part of saturation correction

2024-06-29 21:31:58 +08:00

Crop

finish reconstruction and pass simulation

2024-06-28 19:38:36 +08:00

Demosaic

just make a little part of saturation correction

2024-06-29 21:31:58 +08:00

RAM

finish isp testbench but still have some errors waiting to be deat with

2024-05-15 16:35:17 +08:00

Scaler

update scaler and RAM

2024-05-11 21:53:35 +08:00

sim

just make a little part of saturation correction

2024-06-29 21:31:58 +08:00

.gitignore

update software sim

2024-05-18 18:56:32 +08:00

isp.v

finish GammaCorrection and pass simmulation

2024-06-29 17:05:57 +08:00

xmake.lua

reconstruct some modules

2024-06-27 21:52:46 +08:00

Description

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9.6 MiB

Languages

Verilog 60.1%

C++ 25.7%

SystemVerilog 8.8%

Coq 4.8%

CMake 0.4%

Other 0.1%