SikongJueluo
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ISP
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SystemVerilog 62.7%
C++ 23.2%
Makefile 6.2%
Verilog 4.2%
Nix 2.2%
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SikongJueluo 649d34415f
change a little 		2024-07-02 21:59:39 +08:00
Color change a little 2024-07-02 21:59:39 +08:00
Crop finish reconstruction and pass simulation 2024-06-28 19:38:36 +08:00
Demosaic change a little 2024-07-02 21:59:39 +08:00
RAM change a little 2024-07-02 21:59:39 +08:00
Scaler update scaler and RAM 2024-05-11 21:53:35 +08:00
sim change a little 2024-07-02 21:59:39 +08:00
.gitignore update software sim 2024-05-18 18:56:32 +08:00
isp.sv change a little 2024-07-02 21:59:39 +08:00
xmake.lua reconstruct some modules 2024-06-27 21:52:46 +08:00