SikongJueluo
/
ISP
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
36 Commits 1 Branch 0 Tags 11 MiB
Verilog 60.1%
C++ 25.7%
SystemVerilog 8.8%
Coq 4.8%
CMake 0.4%
Other 0.1%
Go to file
SikongJueluo 649d34415f
change a little 		2024-07-02 21:59:39 +08:00
Color change a little 2024-07-02 21:59:39 +08:00
Crop finish reconstruction and pass simulation 2024-06-28 19:38:36 +08:00
Demosaic change a little 2024-07-02 21:59:39 +08:00
RAM change a little 2024-07-02 21:59:39 +08:00
Scaler update scaler and RAM 2024-05-11 21:53:35 +08:00
sim change a little 2024-07-02 21:59:39 +08:00
.gitignore update software sim 2024-05-18 18:56:32 +08:00
isp.sv change a little 2024-07-02 21:59:39 +08:00
xmake.lua reconstruct some modules 2024-06-27 21:52:46 +08:00