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ISP
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SystemVerilog 62.7%
C++ 23.2%
Makefile 6.2%
Verilog 4.2%
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SikongJueluo 5f19fdf275
Grey World pass simulation 		2024-07-04 19:37:53 +08:00
Color Grey World pass simulation 2024-07-04 19:37:53 +08:00
Crop Grey World pass simulation 2024-07-04 19:37:53 +08:00
Demosaic finish Grey World White Balance 2024-07-03 21:50:29 +08:00
RAM finish Grey World White Balance 2024-07-03 21:50:29 +08:00
Scaler update scaler and RAM 2024-05-11 21:53:35 +08:00
sim Grey World pass simulation 2024-07-04 19:37:53 +08:00
.gitignore update software sim 2024-05-18 18:56:32 +08:00
isp.sv finish Grey World White Balance 2024-07-03 21:50:29 +08:00
xmake.lua reconstruct some modules 2024-06-27 21:52:46 +08:00