33 lines
437 B
Verilog
33 lines
437 B
Verilog
`include "isp.v"
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`default_nettype none
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module tb_isp;
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reg clk;
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reg rst_n;
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isp
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(
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.rst_n (rst_n),
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.clk (clk),
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);
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localparam CLK_PERIOD = 10;
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always #(CLK_PERIOD/2) clk=~clk;
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// initial begin
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// $dumpfile("tb_isp.vcd");
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// $dumpvars(0, tb_isp);
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// end
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initial begin
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#1 rst_n<=1'bx;clk<=1'bx;
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#(CLK_PERIOD*3) rst_n<=1;
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#(CLK_PERIOD*3) rst_n<=0;clk<=0;
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$finish(2);
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end
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endmodule
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`default_nettype wire |