69 lines
1.8 KiB
Verilog
69 lines
1.8 KiB
Verilog
`timescale 1ns / 1ps
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module DiffWidthSyncFIFO #(
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parameter reg [7:0] DATA_WIDTH = 8,
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parameter reg [7:0] DATA_DEPTH = 12,
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parameter reg [7:0] READ_DEPTH = 3,
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parameter reg [7:0] WRITE_DEPTH = 4
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) (
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input wire clk,
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input wire reset,
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input wire read_ready,
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output reg read_en,
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output reg [DATA_WIDTH * READ_DEPTH - 1 : 0] read_data,
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output reg write_ready,
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input wire write_en,
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input wire [DATA_WIDTH * WRITE_DEPTH - 1 : 0] write_data
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);
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reg [DATA_WIDTH - 1 : 0] data[DATA_DEPTH];
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wire [7:0] occupancy;
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reg [7:0] cnt_read, cnt_write;
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reg [7:0] wi, ri;
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assign occupancy = (cnt_write >= cnt_read)
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? (cnt_write - cnt_read)
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: (cnt_write + DATA_DEPTH - cnt_read);
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// write data to fifo
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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write_ready <= 0;
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cnt_write <= 0;
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end else begin
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if (write_en) begin
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write_ready <= 0;
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for (wi = 0; wi < WRITE_DEPTH; wi = wi + 1) begin
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data[cnt_write] <= write_data[DATA_WIDTH*(wi+1)-1 : wi*DATA_WIDTH];
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if (cnt_write < DATA_DEPTH - 1) cnt_write <= cnt_write + 1;
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else cnt_write <= 0;
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end
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end else begin
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write_ready <= 1;
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end
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end
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end
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always @(posedge clk or posedge reset) begin
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if (reset) begin
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read_data <= 0;
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cnt_read <= 0;
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end else begin
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if (read_ready) begin
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read_en <= 1;
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for (ri = 0; ri < READ_DEPTH; ri = ri + 1) begin
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read_data[DATA_WIDTH*(ri+1)-1:ri*DATA_WIDTH] <= data[cnt_read];
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if (cnt_read < DATA_DEPTH - 1) cnt_read <= cnt_read + 1;
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else cnt_read <= 0;
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end
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end else begin
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read_en <= 0;
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end
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end
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end
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endmodule
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