`timescale 1ns / 1ps

module DiffWidthSyncFIFO #(
    parameter reg [7:0] DATA_WIDTH  = 8,
    parameter reg [7:0] DATA_DEPTH  = 12,
    parameter reg [7:0] READ_DEPTH  = 3,
    parameter reg [7:0] WRITE_DEPTH = 4
) (
    input wire clk,
    input wire reset,

    input wire read_ready,
    output reg read_en,
    output reg [DATA_WIDTH * READ_DEPTH - 1 : 0] read_data,

    output reg write_ready,
    input wire write_en,
    input wire [DATA_WIDTH * WRITE_DEPTH - 1 : 0] write_data
);
  reg [DATA_WIDTH - 1 : 0] data[DATA_DEPTH];
  wire [7:0] occupancy;
  reg [7:0] cnt_read, cnt_write;
  reg [7:0] wi, ri;

  assign occupancy = (cnt_write >= cnt_read)
                     ? (cnt_write - cnt_read)
                     : (cnt_write + DATA_DEPTH - cnt_read);

  // write data to fifo
  always @(posedge clk or posedge reset) begin
    if (reset) begin
      write_ready <= 0;
      cnt_write   <= 0;
    end else begin
      if (write_en) begin
        write_ready <= 0;
        for (wi = 0; wi < WRITE_DEPTH; wi = wi + 1) begin
          data[cnt_write] <= write_data[DATA_WIDTH*(wi+1)-1 : wi*DATA_WIDTH];

          if (cnt_write < DATA_DEPTH - 1) cnt_write <= cnt_write + 1;
          else cnt_write <= 0;
        end
      end else begin
        write_ready <= 1;
      end
    end
  end

  always @(posedge clk or posedge reset) begin
    if (reset) begin
      read_data <= 0;
      cnt_read  <= 0;
    end else begin
      if (read_ready) begin
        read_en <= 1;
        for (ri = 0; ri < READ_DEPTH; ri = ri + 1) begin
          read_data[DATA_WIDTH*(ri+1)-1:ri*DATA_WIDTH] <= data[cnt_read];

          if (cnt_read < DATA_DEPTH - 1) cnt_read <= cnt_read + 1;
          else cnt_read <= 0;
        end
      end else begin
        read_en <= 0;
      end
    end
  end

endmodule