30 lines
587 B
Verilog
30 lines
587 B
Verilog
module SDRAM (
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input wire clk,
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input wire read_en,
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input wire [31:0] read_addr,
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output wire [31:0] read_data,
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output wire read_ready,
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input wire write_en,
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input wire [31:0] write_addr,
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input reg [31:0] write_data,
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output wire write_ready
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);
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reg [31:0] ram[1920*1080];
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assign read_ready = (!read_en) ? 1 : 0;
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assign write_ready = (!write_en) ? 1 : 0;
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always @(posedge clk) begin
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if (read_en)
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ram[read_addr] <= read_data;
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end
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always @(posedge clk) begin
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if (write_en)
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write_data <= ram[write_addr];
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end
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endmodule
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