30 lines
587 B
Coq
30 lines
587 B
Coq
|
module SDRAM (
|
||
|
|
input wire clk,
|
||
|
|
|
||
|
|
input wire read_en,
|
||
|
|
input wire [31:0] read_addr,
|
||
|
|
output wire [31:0] read_data,
|
||
|
|
output wire read_ready,
|
||
|
|
|
||
|
|
input wire write_en,
|
||
|
|
input wire [31:0] write_addr,
|
||
|
|
input reg [31:0] write_data,
|
||
|
|
output wire write_ready
|
||
|
|
);
|
||
|
|
reg [31:0] ram[1920*1080];
|
||
|
|
|
||
|
|
assign read_ready = (!read_en) ? 1 : 0;
|
||
|
|
assign write_ready = (!write_en) ? 1 : 0;
|
||
|
|
|
||
|
|
always @(posedge clk) begin
|
||
|
|
if (read_en)
|
||
|
|
ram[read_addr] <= read_data;
|
||
|
|
end
|
||
|
|
|
||
|
|
always @(posedge clk) begin
|
||
|
|
if (write_en)
|
||
|
|
write_data <= ram[write_addr];
|
||
|
|
end
|
||
|
|
|
||
|
|
endmodule
|